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january 2012 i ? 2012 microsemi corporation accelerator series fpgas ? act 3 family features ? up to 10,000 gate array equivalent gates (up to 25,000 equivalent pld gates) ? highly predictable performance with 100% automatic place- and-route ? as low as 9.0 ns clock-to-output times (?1 speed grade) ? up to 186 mhz on-chip performance (?1 speed grade) ? up to 228 user-programmable i/o pins ? four fast, low-skew clock networks ? more than 500 macro functions ? replaces up to twenty 32 macro-cell cplds ? replaces up to one hundred 20-pin pal ? packages ? up to 1,153 dedicated flip-flops ? vqfp, tqfp, bga, and pqfp packages ? nonvolatile, user programmable ? fully tested prior to shipment ? 5.0 v and 3.3 v versions ? optimized for logic synthesis methodologies ? low power cmos technology table 1 ? act 3 family product information device a1415 a1425 a1440 a1460 a14100 capacity gate array equivalent gate s 1,500 2,500 4,000 6,000 10,000 pld equivalent gates 3,750 6,250 10,000 15,000 25,000 ttl equivalent package (40 gates) 40 60 100 150 250 20-pin pal equivalent packages (100 gates) 15 25 40 60 100 logic modules 200 310 564 848 1,377 s-module 104 160 288 432 697 c-module 96 150 276 416 680 dedicated flip-flops 1 264 360 568 768 1,153 user i/os (maximum) 80 100 140 168 228 maximum performance 2 (worst-case commercial, ?1 speed grade) chip-to-chip 3 (mhz) 80 80 80 78 76 accumulators (16-bit, mhz) 47 47 47 47 47 loadable counter (16-bit, mhz) 82 82 82 82 78 prescaled loadable counters (16-bit, mhz) 186 186 186 150 150 datapath, shift registers (mhz) 186 186 186 150 150 clock-to-output (pad-to-p ad, ns) 9.0 9.0 9.5 10.0 10.5 packages 4 (by pin count) cpga plcc pqfp rqfp vqfp tqfp bga cqfp pg100 5 pl84 pq100 ? vq100 ? ? ? pg133 5 pl84 pq100, pq160 ? vq100 ? ? cq132 pg175 5 pl84 pq160 ? vq100 tq176 ? ? pg207 ? pq160, pq208 ? ? tq176 bg225 5 cq196 pg257 ? ? rq208 ? ? bg313 cq256 notes: 1. one flip-flop per s0module, two flip-flops per i/o module. 2. based on a1415a-1, a1425a-1, a1440a-1, a1460a-1, and a14100a-1. 3. clock-to-output (pad -to-pad) + assumed trace delay + setup time. refer to the "system performance model" on page 1-1 and table 1-1 on page 1-2 . 4. see the "product plan" table on page iii for package availability. 5. discontinued device and package combination. 6. ?2 and ?3 speed grades have been discontinued. for more information about discontinued devices, refer to the product discontinuation notices (pdns) listed below, avai lable on the microsemi so c products group website: pdn march 2001 , pdn 0104, pdn 0203 , pdn 0604 , pdn 1004 revision 3
accelerator series fpgas ? act 3 family ii revision 3 ordering information notes: 1. the ?2 and ?3 speed grades have been discontinued. 2. the ceramic pin grid array packages pg100, pg133, and pg 175 have been discontinued in all device densities, speed grades, and temp erature grades. 3. the plastic ball grid array package bg225 has been discontinued in all device densities (specifically for a1460a), all speed grades, and all temperature grades. 4. military grade devices are no long er available for the a1440a device. 5. for more information about discontinued devices, refer to t he product discontinuation notices (pdns) listed below, available on the microsemi soc products group website: pdn march 2001 pdn 0104 pdn 0203 pdn 0604 pdn 1004 _ part number speed grade package type package lead count c = commercial (0 to +70c) i = industrial (?40 to +85c) m = military (?55 to +125c) b = mil-std-883 application (temperature range) pg = ceramic pin grid array pl = plastic leaded chip carrier pq = plastic quad flatpack rq = plastic power quad flatpack vq = very thin (1.0 mm) quad flatpack tq = thin (1.4 mm) quad flatpack cq = ceramic quad flatpack bg = plastic ball grid array std = standard speed ?1 = approximately 15% faster than standard ?2 = approximately 25% faster than standard ?3 = approximately 35% faster than standard a1415a = 1,500 gates a14v15a = 1,500 gates (3.3 v) a1425a = 2,500 gates a14v25a = 2,500 gates (3.3 v) a1440a = 4,000 gates a14v40a = 4,000 gates (3.3 v) a1460a = 6,000 gates a14v60a = 6,000 gates (3.3 v) a14100a = 10,000 gates a14v100a = 10,000 gates (3.3 v) a14100 1 die revision a = 1.0 mm cmos process a rq 208 g c lead-free packaging blank = standard packaging g = rohs compliant packaging
accelerator series fpgas ? act 3 family revision 3 iii product plan device/package speed grade 1 application 1 std. ?1 ?2 ?3 c i m b a1415a device 84-pin plastic leaded chip carrier (plcc) ?? dd ?? ? ? 100-pin plastic quad flatpack (pqfp) ?? dd ?? ? ? 100-pin very thin quad flatpack (vqfp) ?? dd ?? ? ? 100-pin ceramic pin grid array (cpga) d d d d d ? ? ? a14v15a device 84-pin plastic leaded chip carrier (plcc) ? ??? ? ??? 100-pin very thin quad flatpack (vqfp) ? ??? ? ??? a1425a device 84-pin plastic leaded chip carrier (plcc) ?? dd ?? 100-pin plastic quad flatpack (pqfp) ?? dd ?? ?? 100-pin very thin quad flatpack (vqfp) ?? dd ?? ?? 132-pin ceramic quad flatpack (cqfp) ?? ?? ? ? ?? 133-pin ceramic pin grid array (cpga) d d d d d ? d d 160-pin plastic quad flatpack (pqfp) ?? dd ?? ?? a14v25a device 84-pin plastic leaded chip carrier (plcc) ? ??? ? ??? 100-pin very thin quad flatpack (vqfp) ? ??? ? ??? 160-pin plastic quad flatpack (pqfp) ? ??? ? ??? a1440a device 84-pin plastic leaded chip carrier (plcc) ?? dd ?? ?? 100-pin very thin quad flatpack (vqfp) ?? dd ?? ?? 160-pin plastic quad flatpack (pqfp) ?? dd ?? ?? 175-pin ceramic pin grid array (cpga) d d d d d ? ? ? 176-pin thin quad flatpack (tqfp) ?? dd ? ? ?? notes: 1. applications: c = commercial i = industrial m = military 2. commercial only availability: ? = available p = planned ? = not planned d = discontinued speed grade: ?1 = approx. 15% faster than std. ?2 = approx. 25% faster than std. ?3 = approx. 35% faster than std. (?2 and ?3 speed grades have been discontinued.)
accelerator series fpgas ? act 3 family iv revision 3 a14v40a device 84-pin plastic leaded chip carrier (plcc) ? ??? ? ??? 100-pin very thin quad flatpack (vqfp) ? ??? ? ??? 160-pin plastic quad flatpack (pqfp) ? ??? ? ??? 176-pin thin quad flatpack (tqfp) ? ??? ? ??? a1460a device 160-pin plastic quad flatpack (pqfp) ?? dd ?? ?? 176-pin thin quad flatpack (tqfp) ?? dd ?? ?? 196-pin ceramic quad flatpack (cqfp) ?? ?? ? ? ?? 207-pin ceramic pin grid array (cpga) ?? dd ? ? ?? 208-pin plastic quad flatpack (pqfp) ?? dd ?? ?? 225-pin plastic ball grid array (bga) d d d d d ??? a14v60a device 160-pin plastic quad flatpack (pqfp) ? ??? ? ??? 176-pin thin quad flatpack (tqfp) ? ??? ? ??? 208-pin plastic quad flatpack (pqfp) ? ??? ? ??? a14100a device 208-pin power quad flatpack (rqfp) ?? dd ?? ?? 257-pin ceramic pin grid array (cpga) ?? dd ? ? ?? 313-pin plastic ball grid array (bga) ?? dd ? ??? 256-pin ceramic quad flatpack (cqfp) ?? ?? ? ? ?? a14v100a device 208-pin power quad flatpack (rqfp) ? ??? ? ??? 313-pin plastic ball grid array (bga) ? ??? ? ??? device/package speed grade 1 application 1 std. ?1 ?2 ?3 c i m b notes: 1. applications: c = commercial i = industrial m = military 2. commercial only availability: ? = available p = planned ? = not planned d = discontinued speed grade: ?1 = approx. 15% faster than std. ?2 = approx. 25% faster than std. ?3 = approx. 35% faster than std. (?2 and ?3 speed grades have been discontinued.)
accelerator series fpgas ? act 3 family revision 3 v plastic device resources hermetic device resources contact your local microsemi soc products group (for merly actel) representative for device availability: http://www.microsemi.com/soc/contact/default.aspx . device series logic modules gates user i/os pl84 pq100 pq160 pq/rq208 vq100 tq176 bg225* bg313 a1415 200 1500 70 80 ? ? 80 ? ? ? a1425 310 2500 70 80 100 ? 83 ? ? ? a1440 564 4000 70 ? 131 ? 83 140 ? ? a1460 848 6000 ? ? 131 167 ? 151 168 ? a14100 1377 10000 ? ? ? 175 ? ? ? 228 note: *discontinued device series logic modules gates user i/os pg100* pg133* pg175* pg207 pg257 cq132 cq196 cq256 a1415 200 1500 80 ? ? ? ? ? ? ? a1425 310 2500 ? 100 ? ? ? 100 ? ? a1440 564 4000 ? ? 140 ? ? ? ? ? a1460 848 6000 ? ? ? 168 ? ? 168 ? a14100 1377 10000 ? ? ? ? 228 ? ? 228 note: *discontinued
table of contents vi revision 3 act 3 family overview general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 detailed specifications topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 logic modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 i/os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 clock networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 routing structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 5 v operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 3.3 v operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 act 3 timing model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42 package pin assignments pl84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 pq100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 pq160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 pq208, rq208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 vq100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 cq132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 cq196 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 cq256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 bg225 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20 bg313 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22 pg100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 pg133 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 pg175 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 pg207 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30 pg257 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 datasheet information list of changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 datasheet categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 safety critical, life support, and high-reliability applications policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
revision 3 1-1 1 ? act 3 family overview general description microsemi?s act 3 accelerator series of fpgas offers the industry?s fastest high-capacity programmable logic device. act 3 fpgas offer a high performance, pci compliant programmable solution capable of 186 mhz on-chip performance and 9.0 nanosecond clock-to-output (?1 speed grade), with capacities spanning from 1,500 to 10,000 gate array equivalent gates. the act 3 family builds on the proven two-module architecture consisting of combinatorial and sequential logic modules used in microsemi?s 3200dx and 1200xl families. in addition, the act 3 i/o modules contain registers which deliver 9.0 nanos econd clock-to-out times (?1 speed grade). the devices contain four clock distribution networks, including dedicated array and i/o clocks, supporting very fast synchronous and asynchronous designs. in addition, routed clocks c an be used to drive high fanout signals such as flip-flop resets and output. the act 3 family is supported by microsemi?s de signer series development system which offers automatic placement and rout ing (with automatic or fixed pin assign ments), static timing analysis, user programming, and debug and diagnostic probe capabilities. system performance model figure 1-1 ? predictable performance (worst-case commercial, ?1 speed grade) accumulators (16-bit) loadable counters (16-bit) prescaled loadable counters (16-bit) shift registers 186 mhz 82 mhz 47 mhz 186 mhz chip #2 i/o module chip #1 i/o module 35 pf i/o clk i/o clk t ckhs t trace t insu
act 3 family overview 1-2 revision 3 table 1-1 ? chip-to-chip performance (worst-case commercial) device and speed grade t ckhs (ns) t trace (ns) t insu (ns) total (ns) mhz a1425a -3 7.5 1.0 1.8 10.3 97 a1460a -3 9.0 1.0 1.3 11.3 88 a1425a -2 7.5 1.0 2.0 10.5 95 a1460a -2 9.0 1.0 1.5 11.5 87 a1425a -1 9.0 1.0 2.3 12.3 81 a1460a -1 10.0 1.0 1.8 12.8 78 a1425a std 10.0 1.0 2.7 13.7 73 a1460a std 11.5 1.0 2.0 14.5 69 note: the ?2 and ?3 speed grades have been discontinued. refer to pdn 0104 , pdn 0203 , pdn 0604, and pdn 1004 at http://www.microsemi.com/soc/suppor t/notifications/default.aspx#pdn .
revision 3 2-1 2 ? detailed specifications this section of the datasheet is me ant to familiarize the user with the architecture of the act 3 family of fpga devices. a generic description of the family will be presented first, followed by a detailed description of the logic blo cks, the routing structure, the antifuses, and the spec ial function circuits. the on-chip circuitry required to program the devices is not covered. topology the act 3 family architecture is composed of si x key elements: logic modules, i/o modules, i/o pad drivers, routing tracks, clock networks, and prog ramming and test circuits. the basic structure is similar for all devices in the family, differing only in the number of rows, columns, and i/os. the array itself consists of alternating ro ws of modules and channels. the logic modules and channels are in the center of the array; the i/o modules are locat ed along the array periphery. a simplified floor plan is depicted in figure 2-1 . figure 2-1 ? generalized floor plan of act 3 device io io io io io io c scssioio c c scssioio c c scssioio c bio io io io io io io io bin s c c s s io io bin s c c s s io io bin s c c s s io io io clkm io io io io io io io bin s c io cs sc scssioio c an array with n rows and m columns to p i / o s bottom i/os left i/os right i/os rows n+1 n n?1 ? ? ? 2 1 0 channels n+1 n n?1 ? ? ? 2 1 0 n+2 0 1 2 3 4 5 c?1 c c+1 m m+1 m+2 m+3 columns
detailed specifications 2-2 revision 3 logic modules act 3 logic modules are enhanced versions of the 1200xl family logic modules. as in the 1200xl family, there are two types of mo dules: c-modules and s-modules ( figure 2-2 and figure 2-3 ). the c- module is functionally equivalent to the 1200xl c-module and implements high fanin combinatorial macros, such as 5-input and, 5-input or, and so on . it is available for use as the cm8 hard macro. the s-module is designed to implement high-spee d sequential functions within a single module. s-modules consist of a full c-module driving a flip-flo p, which allows an additional level of logic to be implemented without additional propagation delay. it is available for use as the dfm8a/b and dlm8a/b hard macros. c-modules and s-modul es are arranged in pairs called module-pairs. module-pairs are arranged in alternating patterns and make up the bulk of the array. this arrangement allows the placement software to support two-module macros of four types (cc, cs, sc, and ss). the c-module implements the following function: y = !s1 * !s0 * d00 + !s1 * s0 * d01 + s1 * !s0 * d10 + s1 * s0 * d11 eq 1 where: s0 = a0 * b0 and s1 = a1 + b1 figure 2-2 ? c-module diagram figure 2-3 ? s-module diagram d11 d01 d00 d10 a1 b1 a0 b0 y out s1 s0 clr clk d11 d01 d00 d10 a1 b1 a0 b0 y q d out s0 s1
accelerator series fpgas ? act 3 family revision 3 2-3 the s-module contains a full implementation of the c-module plus a clearable sequential element that can either implement a latch or fl ip-flop function. the s-module ca n therefore implement any function implemented by the c-module. this allows co mplex combinatorial-sequential functions to be implemented with no delay penalty. the designer series development system will automatically combine any c-module macro driving an s-module ma cro into the s-module, thereby freeing up a logic module and eliminating a module delay. the clear input clr is accessible from the routing channel. in addition, the clock input may be connected to one of three clock networks: clka, clkb, or hclk. the c-module and s-module functional descriptions are shown in figure 2-2 and figure 2-3 on page 2-2 . the clock selection is determined by a multiplexer select at the clock input to the s-module. i/os i/o modules i/o modules provide an interface between the array a nd the i/o pad drivers. i/o modules are located in the array and access the routing channels in a similar fashion to logic modules. the i/o module schematic is shown in figure 4. the signals da tain and dataout connect to the i/o pad driver. each i/o module contains two d-type flip-flops. ea ch flip-flop is connected to the dedicated i/o clock (ioclk). each flip-flop can be bypa ssed by nonsequential i/os. in additi on, each flip-flop contains a data enable input that can be accessed from the routing channels (ode and ide). the asynchronous preset/clear input is driven by the dedicated preset/clear network (iopcl ). either preset or clear can be selected individually on an i/o module by i/o module basis. figure 2-4 ? functional diagram for i/o module d dataout d q clr/pre datain ioclk iopcl y d q clr/pre ode mux 1 0 mux 1 0 mux 0 1 mux 3 0 1 2 s1 s0
detailed specifications 2-4 revision 3 the i/o module output y is used to bring pad signals into the array or to feed the output register back into the array. this allows the output register to be used in high-speed state machine applications. side i/o modules have a dedicated output segment for y ex tending into the routing channels above and below (similar to logic modules). top/bottom i/o modules have no dedicated output segment. signals coming into the chip from the top or bott om are routed using f-fuses and lvts (f-fuses and lvts are explained in detail in the routing section). i/o pad drivers all pad drivers are capable of being tristate. each buffer connects to an associated i/o module with four signals: oe (output enable), ie (i nput enable), dataout, and datain. certain special signals used only during programming and test also connect to t he pad drivers: outen (global output enable), inen (global input enable), and slew (individual slew selection). see figure 2-5 . special i/os the special i/os are of two types: temporary and permanent. temporary special i/os are used during programming and testing. they function as norma l i/os when the mode pin is inactive. permanent special i/os are user programmed as either normal i/ os or special i/os. their function does not change once the device has been programmed. the permanent special i/os consist of the array clock input buffers (clka and clkb), the hard-wired array clo ck input buffer (hclk), the hard-wired i/o clock input buffer (ioclk), and the hard-wired i/o register pr eset/clear input buffer (iopcl). their function is determined by the i/o macros selected. clock networks the act 3 architecture contains four clock netw orks: two high-performance dedicated clock networks and two general purpose routed networks. the hi gh-performance networks function up to 200 mhz, while the general purpose routed networks function up to 150 mhz. figure 2-5 ? function diagram for i/o pad driver pa d oe slew dataout datain ien inen outen
accelerator series fpgas ? act 3 family revision 3 2-5 dedicated clocks dedicated clock networks support high performance by providing sub-nanosecond skew and guaranteed performance. dedicated clock networks contain no prog ramming elements in the path from the i/o pad driver to the input of s-modules or i/o modules. there are two dedicated clock networks: one for the array registers (hclk), and one for the i/o regist ers (ioclk). the clock networks are accessed by special i/os. the routed clock networks are referred to as clk0 and clk1. each network is connected to a clock module (clkmod) that selects t he source of the clock signal and may be driven as follows ( figure 2-6 ): ? externally from the clka pad ? externally from the clkb pad ? internally from the clkina input ? internally from the clkinb input the clock modules are located in the top row of i/o modules. clock drivers and a dedicated horizontal clock track are located in each horizontal routing chan nel. the function of the clock module is determined by the selection of clock macros from the macro library. the macro clkbuf is used to connect one of the two external clock pins to a clock network, and the macro clkint is used to connect an internally generated clock signal to a clock network. since both clock networks are identical, the user does not care whether clk0 or clk1 is being used. routed clocks can also be used to drive high fanout nets like resets, output enables, or data enables. this saves logic modules and results in performance increases in some cases. routing structure the act 3 architecture uses vertical and horizontal routing tracks to connect the various logic and i/o modules. these routing tracks are metal interconnects that may either be of continuous length or broken into segments. segments can be joined together at the ends using antifuses to increase their lengths up to the full length of the track. figure 2-6 ? clock networks clkb clka from pa d s clock drivers clkmod clkinb clkina s0 s1 internal signal clko(17) clko(16) clko(15) clko(2) clko(1) clock tracks
detailed specifications 2-6 revision 3 horizontal routing horizontal channels are located between the rows of modules and are composed of several routing tracks. the horizontal routing tracks within the channel are divided into one or more segments. the minimum horizontal segment length is the width of a module-pair, and the maximum horizontal segment length is the full length of the channel. any segm ent that spans more than one-third the row length is considered a long horizontal segment. a typical channel is shown in figure 2-7 . undedicated horizontal routing tracks are used to route signal nets. dedica ted routing tracks are used for the global clock networks and for power a nd ground tie-off tracks. vertical routing other tracks run vertically through the modules. vertic al tracks are of three types: input, output, and long. vertical tracks are also divided into one or more segments. each segment in an input track is dedicated to the input of a particular module. each segment in an output track is dedi cated to the output of a particular module. long segments are uncommitt ed and can be assigned during routing. each output segment spans four channels (two above and two bel ow), except near the top and bottom of the array where edge effects occur. lvts contain either one or two segments. an example of vertical routing tracks and segments is shown in figure 2-8 . figure 2-7 ? horizontal routing tracks and segments figure 2-8 ? vertical routing tracks and segments hf module row hclk clk0 nvcc signal signal (lht) signal nvss clk1 track segment | | | | | | | module row vertical input segment s-module c-module vf ff xf module row channel lvts s-module c-module
accelerator series fpgas ? act 3 family revision 3 2-7 antifuse connections an antifuse is a ?normally open? structure as opposed to the normally closed fuse structure used in proms or pals. the use of antifuses to implement a programmable logic device results in highly testable structures as well as an efficient prog ramming architecture. the structure is highly testable because there are no preexisting connections; temporary connections can be made using pass transistors. these temporary connections can isolat e individual antifuses to be programmed as well as isolate individual circuit structures to be tested. this can be done both before and after programming. for example, all metal tracks can be tested for continui ty and shorts between adjacent tracks, and the functionality of all logic modules can be verified. four types of antifuse connections are used in the routing structure of the act 3 array. (the physical structure of the antifuse is identical in each case; only the usage differs.) table 2-1 shows four types of antifuses. examples of all four types of connections are shown in figure 2-7 on page 2-6 and figure 2-8 on page 2-6 . module interface connections to logic and i/o modules are made through vertical segments that connect to the module inputs and outputs. these vertical se gments lie on vertical tracks that span the entire height of the array. module input connections the tracks dedicated to module inputs are segmented by pass transistors in each module row. during normal user operation, the pass transistors are inactive , which isolates the inputs of a module from the inputs of the module directly above or below it. duri ng certain test modes, th e pass transistors are active to verify the continuity of the metal tracks. vertical input segment s span only the channel above or the channel below. the logic modules are arranged such th at half of the inputs are connected to the channel above and half of the inputs to segments in the channel below, as shown in figure 2-9 . table 2-1 ? antifuse types type description xf horizontal-to-vertical connection hf horizontal-to-horizontal connection vf vertical-to-vertical connection ff "fast" vertical connection figure 2-9 ? logic module routing interface y+2 y+1 a1 d10 d11 b1 b0 d01 d00 y- 1 y- 2 lvts y+2 y+1 y y- 1 y- 2 c-modules s-modules d10 b0 a0 d11 a1 b1 d01 a0 y
detailed specifications 2-8 revision 3 module output connections module outputs have dedicated output segments. output segments exte nd vertically two channels above and two channels below, except at the top or bottom of the array. output segm ents twist, as shown in figure 10, so th at only four vertic al tracks are required. lvt connections outputs may also connect to nondedicated segments called long vertical tracks (lvts). each module pair in the array shares four lvts that span the length of the column. any module in the column pair can connect to one of the lvts in the column using an ff connection. the ff connection uses antifuses connected directly to the driver stage of the mo dule output, bypassing the isolation transistor. ff antifuses are programmed at a high er current level than hf, vf, or xf antifuses to produce a lower resistance value. antifuse connections in general every intersection of a vertical segm ent and a horizontal segment contains an unprogrammed antifuse (xf-type). one exception is in the case of the clock networks. clock connections to minimize loading on the clock networks, a subset of inputs has antifuses on the clock tracks. only a few of the c-module and s-module inputs can be co nnected to the clock networks. to further reduce loading on the clock network, only a subset of the horizo ntal routing tracks can connect to the clock inputs of the s-module. programming and test circuits the array of logic and i/o modules is surrounded by test and programming circuits controlled by the temporary special i/o pins mode, sdi, and dclk. the fu nction of these pins is similar to all act family devices. the act 3 family also includes support for two actionprobe ? circuits, allowing complete observability of any logic or i/o module in the array using the temporary special i/o pins, pra and prb.
accelerator series fpgas ? act 3 family revision 3 2-9 5 v operating conditions table 2-2 ? absolute maximum ratings 1 , free air temperature range symbol parameter limits units vcc dc supply voltage ?0.5 to +7.0 v vi input voltage ?0.5 to vcc + 0.5 v vo output voltage ?0.5 to vcc + 0.5 v iio i/o source sink current 2 20 ma t stg storage temperature ?65 to +150 c notes: 1. stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. device should not be operated outside the recommended operating conditions. 2. device inputs are normally high impedance and draw extremely low current. however, when input voltage is greater than vcc + 0.5 v for less than gnd ?0.5 v, the internal protection diodes will forward bias and can draw excessive current. table 2-3 ? recommended operating conditions parameter commercial industrial military units temperature range* 0 to +70 ?40 to +85 ?55 to +125 c 5 v power supply tolerance 5 10 10 %vcc note: *ambient temperature (t a ) is used for commercial and indus trial; case temperature (t c ) is used for military. table 2-4 ? electrical specifications symbol parameter test condition commercial industrial military units min. max. min. max. min. max. voh 1,2 high level output ioh = ?4 ma (cmos) ? ? 3.7 ? 3.7 ? v ioh = ?6 ma (cmos) 3.84 v ioh = ?10 ma (ttl) 3 2.40 v vol 1,2 low level output iol = +6 ma (cmos) 0.33 0.4 0.4 v iol = +12 ma (ttl) 3 0.50 vih high level input ttl inputs 2.0 vcc + 0.3 2.0 vcc + 0.3 2.0 vcc + 0.3 v vil low level input ttl inputs ?0.3 0.8 ?0.3 0.8 ?0.3 0.8 v iin input leakage vi = vcc or gnd ?10 +10 ?10 +10 ?10 +10 a ioz 3-state output leakage vo = vcc or gnd ?10 +10 ?10 +10 ?10 +10 a c io i/o capacitance 3,4 10 10 10 pf icc(s) standby vcc supply curr ent (typical = 0.7 ma) 2 10 20 ma icc(d) dynamic vcc supply current. se e the power dissipation section. notes: 1. microsemi devices can drive and receive either cmos or tt l signal levels. no assignment of i/os as ttl or cmos is required. 2. tested one output at a time, vcc = minimum. 3. not tested; for information only. 4. vout = 0 v, f = 1 mhz 5. typical standby current = 0.7 ma. all outputs unloaded. all inputs = vcc or gnd.
detailed specifications 2-10 revision 3 3.3 v operating conditions table 2-5 ? absolute maximum ratings 1 , free air temperature range symbol parameter limits units vcc dc supply voltage ?0.5 to +7.0 v vi input voltage ?0.5 to vcc + 0.5 v vo output voltage ?0.5 to vcc + 0.5 v iio i/o source sink current 2 20 ma t stg storage temperature ?65 to +150 c notes: 1. stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. device should not be operated outside the recommended operating conditions. 2. device inputs are normally high impedance and draw extremely low current. however, when input voltage is greater than vcc + 0.5 v for less than gnd ?0.5 v, the internal protection diodes will forward bias and can draw excessive current. table 2-6 ? recommended operating conditions parameter commercial units temperature range* 0 to +70 c power supply tolerance 3.0 to 3.6 v note: *ambient temperature (t a ) is used for commercial. table 2-7 ? electrical specifications parameter commercial units min. max. voh 1 ioh = ?4 ma 2.15 ? v ioh = ?3.2 ma 2.4 v vol 1 iol = 6 ma 0.4 v vil ?0.3 0.8 v vih 2.0 vcc + 0.3 v input transition time t r , t f 2 vi = vcc or gnd ?10 +10 a c io i/o capacitance 2,3 10 pf standby current, icc 4 (typical = 0.3 ma) 0.75 ma leakage current 5 ?10 10 a 1. only one output tested at a time. vcc = minimum. 2. not tested; for information only. 3. includes worst-case 84-pin plcc package capacitance. vout = 0 v, f - 1 mhz. 4. typical standby current = 0.3 ma. all outputs unloaded. all inputs = vcc or gnd. 5. vo, vin = vcc or gnd
accelerator series fpgas ? act 3 family revision 3 2-11 package thermal characteristics the device junction to case thermal characteristic is jc, and the junction to ambient air characteristic is ja. the thermal characteristics for ja are shown with two different air flow rates. maximum junction temperature is 150 c. a sample calculation of the absolute maximum power dissipation allowed for a cpga 175-pin package at commercial temperature and still air is as follows: eq 2 table 2-8 ? package thermal characteristics package type * pin count jc ja still air ja 300 ft./min. units ceramic pin grid array 100 20 35 17 c/w 133 20 30 15 c/w 175 20 25 14 c/w 207 20 22 13 c/w 257 20 15 8 c/w ceramic quad flatpack 132 13 55 30 c/w 196 13 36 24 c/w 256 13 30 18 c/w plastic quad flatpack 100 13 51 40 c/w 160 10 33 26 c/w 208 10 33 26 c/w very thin quad flatpack 100 12 43 35 c/w thin quad flatpack 176 11 32 25 c/w power quad flatpack 208 0.4 17 13 c/w plastic leaded chip carrier 84 12 37 28 c/w plastic ball grid array 225 10 25 19 c/w 313 10 23 17 c/w note: maximum power dissipation in still air: pq160 = 2.4 w pq208 = 2.4 w pq100 = 1.6 w vq100 = 1.9 w tq176 = 2.5 w pl84 = 2.2 w rq208 = 4.7 w bg225 = 3.2 w bg313 = 3.5 w max. junction temp. (c) max. ambient temp. (c) ? ja c/w ------------------------------------------------------------------------------------------------------------------------------- -------- 150c 70c ? 25c/w ----------------------------------- - 3.2 w ==
detailed specifications 2-12 revision 3 power dissipation p = [icc standby + iactive] * vcc * iol * vol * n + ioh* (vcc ? voh) * m eq 3 where: icc standby is the current flowing when no inputs or outputs are changing iactive is the current flowing due to cmos switching. iol and ioh are ttl sink/source current. vol and voh are ttl level output voltages. n is the number of output s driving ttl loads to vol. m equals the number of outputs driving ttl loads to voh. an accurate determination of n and m is problema tical because their values depend on the design and on the system i/o. the power ca n be divided into two com ponents: static and active. static power component microsemi fpgas have small static power components t hat result in lower power dissipation than pals or plds. by integrating multiple pals/plds into one fpga, an even greater reduction in board-level power dissipation can be achieved. the power due to standby current is typically a small component of the overall power. standby power is calculated in ta b l e 2 - 9 for commercial, worst case conditions. the static power dissipated by ttl loads depends on the number of outputs driving high or low and the dc load current. again, this value is typically small. for instance, a 32-bit bus sinking 4 ma at 0.33 v will generate 42 mw with all outputs driving low, an d 140 mw with all outputs driving high. the actual dissipation will average somewhere between as i/os switch states with time. active power component power dissipation in cmos devices is usually dominated by the active (dynamic) power dissipation. this component is frequency dependent, a function of the logic and the external i/o. active power dissipation results from charging internal chip capacitances of the interconnect, unpr ogrammed antifuses, module inputs, and module outputs, plus external capacitance due to pc board traces and load device inputs. an additional component of the active power dissip ation is the totem-pole current in cmos transistor pairs. the net effect can be associated with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. equivalent capacitance the power dissipated by a cmos circuit can be expressed by eq 4 . power (w) = c eq * vcc 2 * f eq 4 where: c eq is the equivalent capacitance expressed in pf. vcc is the power supply in volts. f is the switching frequency in mhz. table 2-9 ? standby power calculation icc vcc power 2 ma 5.25 v 10.5 mw
accelerator series fpgas ? act 3 family revision 3 2-13 equivalent capacitance is calculated by measuring icc active at a specified frequency and voltage for each circuit component of interest. measurements have been made over a range of frequencies at a fixed value of vcc. equivalent capacitance is frequency independent so that the results may be used over a wide range of operating conditions. equi valent capacitance values are shown in figure 2-10 . to calculate the active power dissipated from the co mplete design, the switch ing frequency of each part of the logic must be known. eq 5 shows a piece-wise linear summation over all components. power =vcc 2 * [(m * c eqm * f m ) modules + (n * c eqi * f n ) inputs + (p * (c eqo + c l ) * f p ) outputs + 0.5 * (q1 * c eqcr * f q1 ) routed_clk1 + (r1 * fq1) routed_clk1 + 0.5 * (q2 * c eqcr * fq2) routed_clk2 + (r 2 * f q2 ) routed_clk2 + 0.5 * (s 1 * c eqcd * f s1 ) dedicated_clk + (s 2 * c eqci * f s2 ) io_clk ] eq 5 where: m = number of logic modules switching at f m n = number of input buffers switching at f n p = number of output buffers switching at f p q1 = number of clock loads on the first routed array clock q2 = number of clock loads on the second routed array clock r 1 = fixed capacitance due to first routed array clock r 2 = fixed capacitance due to second routed array clock s 1 = fixed number of clock loads on the dedicated array clock s 2 = fixed number of clock loads on the dedicated i/o clock c eqm = equivalent capacitance of logic modules in pf c eqi = equivalent capacitance of input buffers in pf c eqo = equivalent capacitance of output buffers in pf c eqcr = equivalent capacitance of routed array clock in pf c eqcd = equivalent capacitance of dedicated array clock in pf c eqci = equivalent capacitance of dedicated i/o clock in pf c l = output lead capacitance in pf f m = average logic module switching rate in mhz f n = average input buffer switching rate in mhz f p = average output buffer switching rate in mhz f q1 = average first routed array clock rate in mhz f q2 = average second routed array clock rate in mhz f s1 = average dedicated array clock rate in mhz f s2 = average dedicated i/o clock rate in mhz table 2-10 ? ceq values for microsemi fpgas item ceq value modules (c eqm ) 6.7 input buffers (c eqi )7.2 output buffers (c eqo ) 10.4 routed array clock buffer loads (c eqcr ) 1.6 dedicated clock buffer loads (c eqcd ) 0.7 i/o clock buffer loads (c eqci) 0.9
detailed specifications 2-14 revision 3 table 2-11 ? fixed capacitance values for microsemi fpgas device type r1, routed_clk1 r2, routed_clk2 a1415a 60 60 a14v15a 57 57 a1425a 75 75 a14v25a 72 72 a1440a 105 105 a14v40a 100 100 a1440b 105 105 a1460a 165 165 a14v60a 157 157 a1460b 165 165 a14100a 195 195 a14v100a 185 185 a14100b 195 195 table 2-12 ? fixed clock loads (s1/s2) device type s1, clock loads on dedicated array clock s2, clock loads on dedicated i/o clock a1415a 104 80 a14v15a 104 80 a1425a 160 100 a14v25a 160 100 a1440a 288 140 a14v40a 288 140 a1440b 288 140 a1460a 432 168 a14v60a 432 168 a1460b 432 168 a14100a 697 228 a14v100a 697 228 a14100b 697 228
accelerator series fpgas ? act 3 family revision 3 2-15 determining average switching frequency to determine the switching frequency for a design, you must have a detailed understanding of the data input values to the circuit. the following guidelines are meant to represent wors t-case scenarios so that they can be generally used to predict the upper lim its of power dissipation. these guidelines are as follows: table 2-13 ? guidelines for predicting power dissipation data value logic modules (m) 80% of modules inputs switching (n) # inputs/4 outputs switching (p) # output/4 first routed array clock loads (q1) 40% of sequential modules second routed array clock loads (q2) 40% of sequential modules load capacitance (cl) 35 pf average logic module switching rate (fm) f/10 average input switching rate (fn) f/5 average output switching rate (fp) f/10 average first routed array clock rate (fq1) f/2 average second routed array clock rate (fq2) f/2 average dedicated array clock rate (fs1) f average dedicated i/o clock rate (f s2 ) f
detailed specifications 2-16 revision 3 act 3 timing model note: values shown for a1425a ?1 speed grade device. figure 2-10 ? timing model output delays internal delays input delays t inh = 0.0 ns t insu = 2.3 ns i/o clock i/o module d q t icky = 6.0 ns f iomax = 150 mhz t iny = 3.6 ns t ird2 = 1.6 ns combinatorial logic module t pd = 2.6 ns sequential logic module i/o module t rd1 = 1.1 ns t dhs = 6.4 ns i/o module array clock f hmax = 150 mhz comb. logic included in t sud d q d q t outh = 0.9 ns t outsu = 0.9 ns t dhs = 6.4 ns t enzhs = 5.1 ns t rd1 = 1.1 ns t co = 2.6 ns t sud = 0.7 ns t hd = 0.0 ns t rd4 = 2.2 ns t rd8 = 3.6 ns predicted routing delays t hckh = 3.9 ns t ckhs = 9.0 ns (pad-pad)
accelerator series fpgas ? act 3 family revision 3 2-17 figure 2-11 ? output buffers figure 2-12 ? ac test loads figure 2-13 ? input buffer delays to ac test loads (shown below) pa d d e tribuff in vcc gnd 50% out vol voh 1.5 v t dhs, 50% 1.5 v t dhs en vcc gnd 50% out vol 1.5 v t enzhs, 50% 10% t enhsz en vcc gnd 50% out gnd voh 1.5 v t enzhs, 50% 90% t enhsz vcc load 1 (used to measure propagation delay) load 2 (used to measure rising/falling edges) 35 pf to the output under test vcc gnd 35 pf to the output under test r to vcc for t plz / t pzl r to gnd for t phz / t pzh r = 1 k pa d y inbuf in 3v 0v 1.5 v out gnd vcc 50% t iny 1.5 v 50% t iny
detailed specifications 2-18 revision 3 figure 2-14 ? module delays figure 2-15 ? sequential module timing characteristics s a b y s, a or b out gnd vcc 50% t pd out gnd gnd vcc 50% 50% 50% vcc 50% 50% t pd t pd t pd flip-flops (positive edge triggered) d clk clr q d clk q clr t wclka t wasyn t hd t sud t a t wclka t co t clr
accelerator series fpgas ? act 3 family revision 3 2-19 figure 2-16 ? i/o module: sequential input timing characteristics figure 2-17 ? i/o module: sequential outp ut timing characteristics (positive edge triggered) d e ioclk clr pre y d ioclk e y pre, clr t iopwh t ioaspw t inh t idesu t insu t iclry t iop t iopwl t icky t ideh q t ckhs, d ioclk e y pre, clr t iopwh t ioaspw t outh t odesu t outsu t oclry t iop t iopwl t ocky tckls (positive edge triggered) d e ioclk clr pre y q t odeh
detailed specifications 2-20 revision 3 tightest delay distributions propagation delay between logic modules depends on t he resistive and capacitive loading of the routing tracks, the interconnect elements, and the module inputs being driven. propagation delay increases as the length of routin g tracks, the number of inte rconnect elements, or the nu mber of inputs increases. from a design perspective, the propagation delay can be statistically correlated or modeled by the fanout (number of loads) driven by a module. higher fanout usually requires some paths to have longer lengths of routing track. the act 3 family delivers the tightest fanout delay distribution of any fpga. this tight distribution is achieved in two ways: by decreas ing the delay of the interconnect elements and by decreasing the number of interconnect elements per path. microsemi?s patented plice antifuse offers a very low resistive/capacitive interconnect. the act 3 family?s antifuses, fabricated in 0.8 micron m lithography, offer nominal levels of 200 resistance and 6 femtofarad (ff) capacitance per ant ifuse. the act 3 fanout distributi on is also tighter than alternative devices due to the low number of antifuses r equired per interconnect path. the act 3 family?s proprietary architecture limits th e number of antifuses per path to only four, with 90% of interconnects using only two antifuses. the act 3 family?s tight fanout delay distribution offe rs an fpga design environment in which fanout can be traded for the increased performance of reduced logic level designs. this also simplifies performance estimates when designing with act 3 devices. timing characteristics timing characteristics for act 3 devices fall into three categories: family dependent, device dependent, and design dependent. the input and output buffer characteristics are common to all act 3 family members. internal routing delays are device depe ndent. design dependency means actual delays are not determined until after placement and routing of t he user?s design is complete. delay values may then be determined by using the als timer utility or performing simulation with post-layout delays. critical nets and typical nets propagation delays are expressed only for typical net s, which are used for initial design performance evaluation. critical net delays can then be applied to the most time-critical paths. critical nets are determined by net property assignment prior to placement and routing. up to 6% of the nets in a design may be designated as critical, while 90% of the nets in a design are typical. long tracks some nets in the design use long tracks. long tra cks are special routing res ources that span multiple rows, columns, or modules. long tracks employ thre e and sometimes four antifuse connections. this increases capacitance and resistance, result ng in longer net delays fo r macros connected to long tracks. typically up to 6% of nets in a fully utilized device require long tracks. long tracks contribute approximately 4 ns to 14 ns delay. this additional delay is represented statistically in higher fanout (fo = 8) routing delays in the datasheet specifications section. table 2-14 ? logic module and routing delay by fanout (ns); worst-case commercial conditions speed grade fo = 1 fo = 2 fo = 3 fo = 4 fo = 8 act 3 ?3 2.9 3.2 3.4 3.7 4.8 act 3 ?2 3.3 3.7 3.9 4.2 5.5 act 3 ?1 3.7 4.2 4.4 4.8 6.2 act 3 std 4.3 4.8 5.1 5.5 7.2 notes: 1. obtained by added t rd(x=fo) to t pd from the logic module timing characteristics tables found in this datasheet. 2. the ?2 and ?3 speed grades have been discontinued. refer to pdn 0104, pdn 0203 , pdn 0604 , and pdn 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn.
accelerator series fpgas ? act 3 family revision 3 2-21 timing derating act 3 devices are manufactured in a cmos process. therefore, device performance varies according to temperature, voltage, and process variations. minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. table 2-15 ? timing derating factor (temperature and voltage) (commercial mini mum/maximum specification) x industrial military min. max. min. max. 0.66 1.07 0.63 1.17 table 2-16 ? timing derating factor for designs at typical temperature (t j = 25c) and voltage (5.0 v) (commercial maximum specification) x 0.85 table 2-17 ? temperature and voltage derating factors (normalized to worst-case commercial, tj = 4.75 v, 70c) ?55?400 257085125 4.50 0.72 0.76 0.85 0.90 1.04 1.07 1.117 4.75 0.70 0.73 0.82 0.87 1.00 1.03 1.12 5.00 0.68 0.71 0.79 0.84 0.97 1.00 1.09 5.25 0.66 0.69 0.77 0.82 0.94 0.97 1.06 5.50 0.63 0.66 0.74 0.79 0.90 0.93 1.01 note: this derating factor applies to all routing and propagation delays. figure 2-18 ? junction temperature and voltage derating curves (normalized to worst-case commercial, tj = 4.75 v, 70c) voltage (v) derating factor 0.60 0.70 0.80 0.90 1.00 1.10 1.20 4.50 4.75 5.00 5.25 5.50
detailed specifications 2-22 revision 3 a1415a, a14v15a ti ming characteristics table 2-18 ? a1415a, a14v15a worst-case commercial conditions, vcc = 4.75 v, t j = 70c 1 logic module propagation delays 2 ?3 speed 3 ?2 speed 3 ?1 speed std. speed 3.3 v speed 1 units parameter/description min. max. min. max. min. max. min. max. min. max. t pd internal array module 2.0 2.3 2.6 3.0 3.9 ns t co sequential clock to q 2.0 2.3 2.6 3.0 3.9 ns t clr asynchronous clear to q 2.0 2.3 2.6 3.0 3.9 ns predicted routing delays 4 t rd1 fo = 1 routing delay 0.9 1.0 1.1 1.3 1.7 ns t rd2 fo = 2 routing delay 1.2 1.4 1.6 1.8 2.4 ns t rd3 fo = 3 routing delay 1.4 1.6 1.8 2.1 2.8 ns t rd4 fo = 4 routing delay 1.7 1.9 2.2 2.5 3.3 ns t rd8 fo = 8 routing delay 2.8 3.2 3.6 4.2 5.5 ns logic module sequential timing t sud flip-flop data input setup 0.5 0.6 0.7 0.8 0.8 ns t hd flip-flop data input hold 0.0 0.0 0.0 0.0 0.0 ns t sud latch data input setup 0.5 0.6 0.7 0.8 0.8 ns t hd latch data input hold 0.0 0.0 0.0 0.0 0.0 ns t wasyn asynchronous pulse widt h 1.9 2.4 3.2 3.8 4.8 ns t wclka flip-flop clock pulse width 1.9 2.4 3.2 3.8 4.8 ns t a flip-flop clock input period 4.0 5.0 6.8 8.0 10.0 ns f max flip-flop clock frequency 250 200 150 125 100 mhz notes: 1. vcc = 3.0 v for 3.3 v specifications. 2. for dual-module macros, use t pd + t rd1 + t pdn + t co + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. 3. the ?2 and ?3 speed grades have been discontinued. please refer to the product discontinuation notices (pdns) listed below: pdn march 2001 pdn 0104 pdn 0203 pdn 0604 pdn 1004 4. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual rout ing delay measurements performed on the device prior to shipment.
accelerator series fpgas ? act 3 family revision 3 2-23 a1415a, a14v15a timing ch aracteristics (continued) table 2-19 ? a1415a, a14v15a worst-case commercial conditions, vcc = 4.75 v, t j = 70c i/o module input propagation delays ?3 speed 1 ?2 speed 1 ?1 speed std. speed 3.3 v speed 2 units parameter/description min. max. min. max. min. m ax. min. max. min. max. t iny input data pad to y 2.8 3.2 3.6 4.2 5.5 ns t icky input reg ioclk pad to y 4.7 5.3 6.0 7.0 9.2 ns t ocky output reg ioclk pad to y 4.7 5.3 6.0 7.0 9.2 ns t iclry input asynchronous clear to y 4.7 5.3 6.0 7.0 9.2 ns t oclry output asynchronous clear to y 4.7 5.3 6.0 7.0 9.2 ns predicted input routing delays 2 t rd1 fo = 1 routing delay 0. 9 1.0 1.1 1.3 1.7 ns t rd2 fo = 2 routing delay 1.2 1.4 1.6 1.8 2.4 ns t rd3 fo = 3 routing delay 1. 4 1.6 1.8 2.1 2.8 ns t rd4 fo = 4 routing delay 1. 7 1.9 2.2 2.5 3.3 ns t rd8 fo = 8 routing delay 2.8 3.2 3.6 4.2 5.5 ns i/o module sequential timing (wrt ioclk pad) t inh input f-f data hold 0. 0 0.0 0.0 0.0 0.0 ns t insu input f-f data setup 2.0 2.3 2.5 3.0 3.0 ns t ideh input data enable hold 0.0 0.0 0.0 0.0 0.0 ns t idesu input data enable setup 5.8 6.5 7.5 8.6 8.6 ns t outh output f-f data hold 0.7 0.8 0.9 1.0 1.0 ns t outsu output f-f data setup 0.7 0.8 0.9 1.0 1.0 ns t odeh output data enable hold 0.3 0.4 0.4 0.5 0.5 ns f odesu output data enable setup 1.3 1.5 1.7 2.0 2.0 ns notes: 1. the ?2 and ?3 speed grades have been discontinued. please refer to the product discontinuation notices (pdns) listed below: pdn march 2001 pdn 0104 pdn 0203 pdn 0604 pdn 1004 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment.
detailed specifications 2-24 revision 3 a1415a, a14v15a timing ch aracteristics (continued) table 2-20 ? a1415a, a14v15a worst-case commercial conditions, vcc = 4.75 v, t j = 70c i/o module ? ttl output timing 1 ?3 speed 2 ?2 speed 2 ?1 speed std. speed 3.3 v speed 1 units parameter/description min. max. min. max. min. m ax. min. max. min. max. t dhs data to pad, high slew 5.0 5.6 6.4 7.5 9.8 ns t dls data to pad, low slew 8.0 9.0 10.2 12.0 15.6 ns t enzhs enable to pad, z to h/l, high slew 4.0 4.5 5.1 6.0 7.8 ns t enzls enable to pad, z to h/l, low slew 7.4 8.3 9.4 11.0 14.3 ns t enhsz enable to pad, h/l to z, high slew 6.5 7.5 8.5 10.0 13.0 ns t enlsz enable to pad, h/l to z, low slew 6.5 7.5 8.5 10.0 13.0 ns t ckhs ioclk pad to pad h/l, hig h slew 7.5 7.5 9.0 10.0 13.0 ns t ckls ioclk pad to pad h/l, low slew 11.3 11.3 13.5 15.0 19.5 ns d tlhhs delta low to high, high slew 0.02 0.02 0.03 0.03 0.04 ns/pf d tlhls delta low to high, low slew 0.05 0.05 0.06 0.07 0.09 ns/pf d thlhs delta high to low, high slew 0.04 0.04 0.04 0.05 0.07 ns/pf d thlls delta high to low, low slew 0.05 0.05 0.06 0.07 0.09 ns/pf i/o module ? cmos output timing 1 t dhs data to pad, high slew 6.2 7.0 7.9 9.3 12.1 ns t dls data to pad, low slew 11.7 13.1 14.9 17.5 22.8 ns t enzhs enable to pad, z to h/l, high slew 5.2 5.9 6.6 7.8 10.1 ns t enzls enable to pad, z to h/l, low slew 8.9 10.0 11.3 13.3 17.3 ns t enhsz enable to pad, h/l to z, high slew 6.7 7.5 8.5 10.0 13.0 ns t enlsz enable to pad, h/l to z, low slew 6.7 7.5 9.0 10.0 13.0 ns t ckhs ioclk pad to pad h/l, high slew 8.9 8.9 10.7 11.8 15.3 ns t ckls ioclk pad to pad h/l, low slew 13.0 13.0 15.6 17.3 22.5 ns d tlhhs delta low to high, high slew 0.04 0.04 0.05 0.06 0.08 ns/pf d tlhls delta low to high, low slew 0.07 0.08 0.09 0.11 0.14 ns/pf d thlhs delta high to low, high slew 0.03 0.03 0.03 0.04 0.05 ns/pf d thlls delta high to low, low slew 0.04 0.04 0.04 0.05 0.07 ns/pf notes: 1. delays based on 35 pf loading. 2. the ?2 and ?3 speed grades have been discontinued. please refer to the product discontinuation notices (pdns) listed below: pdn march 2001 pdn 0104 pdn 0203 pdn 0604 pdn 1004
accelerator series fpgas ? act 3 family revision 3 2-25 a1415a, a14v15a timing ch aracteristics (continued) table 2-21 ? a1415a, a14v15a worst-case commercial conditions, vcc = 4.75 v, t j = 70c dedicated (hardwired) i/o clock network ?3 speed ?2 speed ?1 speed std. speed 3.3 v speed 1 units parameter/description min. max. min. max. min. m ax. min. max. min. max. t iockh input low to high (pad to i/o module input) 2.0 2.3 2.6 3.0 3.5 ns t iopwh minimum pulse width high 1.9 2.4 3.3 3.8 4.8 ns t ipowl minimum pulse width low 1.9 2.4 3.3 3.8 4.8 ns t iosapw minimum asynchronous pulse width 1.9 2.4 3.3 3.8 4.8 ns t iocksw maximum skew 0.4 0.4 0.4 0.4 0.4 ns t iop minimum period 4.0 5.0 6.8 8.0 10.0 ns f iomax maximum frequency 250 200 150 125 100 mhz dedicated (hardwir ed) array clock t hckh input low to high (pad to s-module input) 3.0 3.4 3.9 4.5 5.5 ns t hckl input high to low (pad to s-module input) 3.0 3.4 3.9 4.5 5.5 ns t hpwh minimum pulse width high 1.9 2.4 3.3 3.8 4.8 ns t hpwl minimum pulse width low 1.9 2.4 3.3 3.8 4.8 ns t hcksw delta high to low, low slew 0.3 0.3 0.3 0.3 0.3 ns t hp minimum period 4.0 5.0 6.8 8.0 10.0 ns f hmax maximum frequency 250 200 150 125 100 mhz routed array clock networks t rckh input low to high (fo = 64) 3.7 4.1 4.7 5.5 9.0 ns t rckl input high to low (fo = 64) 4.0 4.5 5.1 6.0 9.0 ns t rpwh min. pulse width high (fo = 64) 3.3 3.8 4.2 4.9 6.5 ns t rpwl min. pulse width low (fo = 64) 3.3 3.8 4.2 4.9 6.5 ns t rcksw maximum skew (fo = 128) 0.7 0.8 0.9 1.0 1.0 ns t rp minimum period (fo = 64) 6.8 8.0 8.7 10.0 13.4 ns f rmax maximum frequency (fo = 64) 150 125 115 100 75 mhz clock-to-clock skews t iohcksw i/o clock to h-clock skew 0.0 1.7 0.0 1.8 0.0 2.0 0.0 2.2 0.0 3.0 ns t iorcksw i/o clock to r-clock skew (fo = 64) 0.0 1.0 0.0 1.0 0.0 1.0 0.0 1.0 0.0 3.0 ns t hrcksw h-clock to r-clock skew (fo = 64) (fo = 50% maximum) 0.0 1.0 0.0 1.0 0.0 1.0 0.0 1.0 0.0 0.0 3.0 3.0 ns notes: 1. delays based on 35 pf loading. 2. the ?2 and ?3 speed grades have been discontinued. refer to pdn 0104 , pdn 0203 , pdn 0604, and pdn 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn .
detailed specifications 2-26 revision 3 a1425a, a14v25a ti ming characteristics table 2-22 ? a1425a, a14v25a worst-case commercial conditions, vcc = 4.75 v, t j = 70c 1 logic module propagation delays 2 ?3 speed 3 ?2 speed 3 ?1 speed std. speed 3.3 v speed 1 units parameter/description min. max. min. max. min. max. min. max. min. max. t pd internal array module 2.0 2.3 2.6 3.0 3.9 ns t co sequential clock to q 2.0 2.3 2.6 3.0 3.9 ns t clr asynchronous clear to q 2.0 2.3 2.6 3.0 3.9 ns predicted routing delays 4 t rd1 fo = 1 routing delay 0.9 1.0 1.1 1.3 1.7 ns t rd2 fo = 2 routing delay 1.2 1.4 1.6 1.8 2.4 ns t rd3 fo = 3 routing delay 1.4 1.6 1.8 2.1 2.8 ns t rd4 fo = 4 routing delay 1.7 1.9 2.2 2.5 3.3 ns t rd8 fo = 8 routing delay 2.8 3.2 3.6 4.2 5.5 ns logic module sequential timing t sud flip-flop data input setup 0.5 0.6 0.7 0.8 0.8 ns t hd flip-flop data input hold 0.0 0.0 0.0 0.0 0.0 ns t sud latch data input setup 0.5 0.6 0.7 0.8 0.8 ns t hd latch data input hold 0.0 0.0 0.0 0.0 0.0 ns t wasyn asynchronous pulse widt h 1.9 2.4 3.2 3.8 4.8 ns t wclka flip-flop clock pulse width 1.9 2.4 3.2 3.8 4.8 ns t a flip-flop clock input period 4.0 5.0 6.8 8.0 10.0 ns f max flip-flop clock frequency 250 200 150 125 100 mhz notes: 1. vcc = 3.0 v for 3.3 v specifications. 2. for dual-module macros, use t pd + t rd1 + t pdn + t co + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. 3. the ?2 and ?3 speed grades have been discontinued. refer to pdn 0104 , pdn 0203 , pdn 0604, and pdn 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn . 4. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual rout ing delay measurements performed on the device prior to shipment.
accelerator series fpgas ? act 3 family revision 3 2-27 a1425a, a14v25a timing ch aracteristics (continued) table 2-23 ? a1425a, a14v25a worst-case commercial conditions, vcc = 4.75 v, t j = 70c i/o module input propagation delays ?3 speed 1 ?2 speed 1 ?1 speed std. speed 3.3 v speed 1 units parameter/description min. max. min. max. min. m ax. min. max. min. max. t iny input data pad to y 2.8 3.2 3.6 4.2 5.5 ns t icky input reg ioclk pad to y 4.7 5.3 6.0 7.0 9.2 ns t ocky output reg ioclk pad to y 4.7 5.3 6.0 7.0 9.2 ns t iclry input asynchronous clear to y 4.7 5.3 6.0 7.0 9.2 ns t oclry output asynchronous clear to y 4.7 5.3 6.0 7.0 9.2 ns predicted input routing delays 2 t rd1 fo = 1 routing delay 0. 9 1.0 1.1 1.3 1.7 ns t rd2 fo = 2 routing delay 1.2 1.4 1.6 1.8 2.4 ns t rd3 fo = 3 routing delay 1. 4 1.6 1.8 2.1 2.8 ns t rd4 fo = 4 routing delay 1. 7 1.9 2.2 2.5 3.3 ns t rd8 fo = 8 routing delay 2.8 3.2 3.6 4.2 5.5 ns i/o module sequential timing (wrt ioclk pad) t inh input f-f data hold 0. 0 0.0 0.0 0.0 0.0 ns t insu input f-f data setup 1.8 2.0 2.3 2.7 3.0 ns t ideh input data enable hold 0.0 0.0 0.0 0.0 0.0 ns t idesu input data enable setup 5.8 6.5 7.5 8.6 8.6 ns t outh output f-f data hold 0.7 0.8 0.9 1.0 1.0 ns t outsu output f-f data setup 0.7 0.8 0.9 1.0 1.0 ns t odeh output data enable hold 0.3 0.4 0.4 0.5 0.5 ns f odesu output data enable setup 1.3 1.5 1.7 2.0 2.0 ns notes: * 1. the ?2 and ?3 speed grades have been discontinued. refer to pdn 0104 , pdn 0203 , pdn 0604, and pdn 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn . 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment.
detailed specifications 2-28 revision 3 a1425a, a14v25a timing ch aracteristics (continued) table 2-24 ? a1425a, a14v25a worst-case commercial conditions, vcc = 4.75 v, t j = 70c i/o module ? ttl output timing 1 ?3 speed 2 ?2 speed 2 ?1 speed std. speed 3.3 v speed 1 units parameter/description min. max. min. max. min. m ax. min. max. min. max. t dhs data to pad, high slew 5.0 5.6 6.4 7.5 9.8 ns t dls data to pad, low slew 8.0 9.0 10.2 12.0 15.6 ns t enzhs enable to pad, z to h/l, high slew 4.0 4.5 5.1 6.0 7.8 ns t enzls enable to pad, z to h/l, low slew 7.4 8.3 9.4 11.0 14.3 ns t enhsz enable to pad, h/l to z, high slew 6.5 7.5 8.5 10.0 13.0 ns t enlsz enable to pad, h/l to z, low slew 6.5 7.5 8.5 10.0 13.0 ns t ckhs ioclk pad to pad h/l, hig h slew 7.5 7.5 9.0 10.0 13.0 ns t ckls ioclk pad to pad h/l, low slew 11.3 11.3 13.5 15.0 19.5 ns d tlhhs delta low to high, high slew 0.02 0.02 0.03 0.03 0.04 ns/pf d tlhls delta low to high, low slew 0.05 0.05 0.06 0.07 0.09 ns/pf d thlhs delta high to low, high slew 0.04 0.04 0.04 0.05 0.07 ns/pf d thlls delta high to low, low slew 0.05 0.05 0.06 0.07 0.09 ns/pf i/o module ? cmos output timing 1 t dhs data to pad, high slew 6.2 7.0 7.9 9.3 12.1 ns t dls data to pad, low slew 11.7 13.1 14.9 17.5 22.8 ns t enzhs enable to pad, z to h/l, high slew 5.2 5.9 6.6 7.8 10.1 ns t enzls enable to pad, z to h/l, low slew 8.9 10.0 11.3 13.3 17.3 ns t enhsz enable to pad, h/l to z, high slew 6.7 7.5 8.5 10.0 13.0 ns t enlsz enable to pad, h/l to z, low slew 6.7 7.5 9.0 10.0 13.0 ns t ckhs ioclk pad to pad h/l, high slew 8.9 8.9 10.7 11.8 15.3 ns t ckls ioclk pad to pad h/l, low slew 13.0 13.0 15.6 17.3 22.5 ns d tlhhs delta low to high, high slew 0.04 0.04 0.05 0.06 0.08 ns/pf d tlhls delta low to high, low slew 0.07 0.08 0.09 0.11 0.14 ns/pf d thlhs delta high to low, high slew 0.03 0.03 0.03 0.04 0.05 ns/pf d thlls delta high to low, low slew 0.04 0.04 0.04 0.05 0.07 ns/pf notes: * 1. delays based on 35 pf loading. 2. the ?2 and ?3 speed grades have been discontinued. refer to pdn 0104 , pdn 0203 , pdn 0604, and pdn 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn .
accelerator series fpgas ? act 3 family revision 3 2-29 a1425a, a14v25a timing ch aracteristics (continued) table 2-25 ? a1425a, a14v25a worst-case commercial conditions, vcc = 4.75 v, t j = 70c dedicated (hardwired) i/o clock network ?3 speed 1 ?2 speed 1 ?1 speed std. speed 3.3 v speed 1 units parameter/description min. max. min. max. min. m ax. min. max. min. max. t iockh input low to high (pad to i/o module input) 2.0 2.3 2.6 3.0 3.5 ns t iopwh minimum pulse width high 1.9 2.4 3.3 3.8 4.8 ns t ipowl minimum pulse width low 1.9 2.4 3.3 3.8 4.8 ns t iosapw minimum asynchronous pulse width 1.9 2.4 3.3 3.8 4.8 ns t iocksw maximum skew 0.4 0.4 0.4 0.4 0.4 ns t iop minimum period 4.0 5.0 6.8 8.0 10.0 ns f iomax maximum frequency 250 200 150 125 100 mhz dedicated (hardwir ed) array clock t hckh input low to high (pad to s-module input) 3.0 3.4 3.9 4.5 5.5 ns t hckl input high to low (pad to s-module input) 3.0 3.4 3.9 4.5 5.5 ns t hpwh minimum pulse width high 1.9 2.4 3.3 3.8 4.8 ns t hpwl minimum pulse width low 1.9 2.4 3.3 3.8 4.8 ns t hcksw delta high to low, low slew 0.3 0.3 0.3 0.3 0.3 ns t hp minimum period 4.0 5.0 6.8 8.0 10.0 ns f hmax maximum frequency 250 200 150 125 100 mhz routed array clock networks t rckh input low to high (fo = 64) 3.7 4.1 4.7 5.5 9.0 ns t rckl input high to low (fo = 64) 4.0 4.5 5.1 6.0 9.0 ns t rpwh min. pulse width high (fo = 64) 3.3 3.8 4.2 4.9 6.5 ns t rpwl min. pulse width low (fo = 64) 3.3 3.8 4.2 4.9 6.5 ns t rcksw maximum skew (fo = 128) 0.7 0.8 0.9 1.0 1.0 ns t rp minimum period (fo = 64) 6.8 8.0 8.7 10.0 13.4 ns f rmax maximum frequency (fo = 64) 150 125 115 100 75 mhz clock-to-clock skews t iohcksw i/o clock to h-clock skew 0.0 1.7 0.0 1.8 0.0 2.0 0.0 2.2 0.0 3.0 ns t iorcksw i/o clock to r-clock skew (fo = 64) (fo = 80) 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 3.0 3.0 ns t hrcksw h-clock to r-clock skew (fo = 64) (fo = 80) 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 ns notes: 1. the ?2 and ?3 speed grades have been discontinued. refer to pdn 0104 , pdn 0203 , pdn 0604, and pdn 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn . 2. delays based on 35 pf loading.
detailed specifications 2-30 revision 3 a1440a, a14v40a ti ming characteristics table 2-26 ? a1440a, a14v40a worst-case commercial conditions, vcc = 4.75 v, t j = 70c 1 logic module propagation delays 2 ?3 speed 3 ?2 speed 3 ?1 speed std. speed 3.3 v speed 1 units parameter/description min. max. min. max. min. max. min. max. min. max. t pd internal array module 2.0 2.3 2.6 3.0 3.9 ns t co sequential clock to q 2.0 2.3 2.6 3.0 3.9 ns t clr asynchronous clear to q 2.0 2.3 2.6 3.0 3.9 ns predicted routing delays 4 t rd1 fo = 1 routing delay 0.9 1.0 1.1 1.3 1.7 ns t rd2 fo = 2 routing delay 1.2 1.4 1.6 1.8 2.4 ns t rd3 fo = 3 routing delay 1.4 1.6 1.8 2.1 2.8 ns t rd4 fo = 4 routing delay 1.7 1.9 2.2 2.5 3.3 ns t rd8 fo = 8 routing delay 2.8 3.2 3.6 4.2 5.5 ns logic module sequential timing t sud flip-flop data input setup 0.5 0.6 0.7 0.8 0.8 ns t hd flip-flop data input hold 0.0 0.0 0.0 0.0 0.0 ns t sud latch data input setup 0.5 0.6 0.7 0.8 0.8 ns t hd latch data input hold 0.0 0.0 0.0 0.0 0.0 ns t wasyn asynchronous pulse widt h 1.9 2.4 3.2 3.8 4.8 ns t wclka flip-flop clock pulse width 1.9 2.4 3.2 3.8 4.8 ns t a flip-flop clock input period 4.0 5.0 6.8 8.0 10.0 ns f max flip-flop clock frequency 250 200 150 125 100 mhz notes: 1. vcc = 3.0 v for 3.3 v specifications. 2. for dual-module macros, use t pd + t rd1 + t pdn + t co + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. 3. the ?2 and ?3 speed grades have been discontinued. refer to pdn 0104 , pdn 0203 , pdn 0604, and pdn 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn . 4. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual rout ing delay measurements performed on the device prior to shipment.
accelerator series fpgas ? act 3 family revision 3 2-31 a1440a, a14v40a timing ch aracteristics (continued) table 2-27 ? a1440a, a14v40a worst-case commercial conditions, vcc = 4.75 v, t j = 70c i/o module input propagation delays ?3 speed 1 ?2 speed 1 ?1 speed std. speed 3.3 v speed 1 units parameter/description min. max. min. max. min. m ax. min. max. min. max. t iny input data pad to y 2.8 3.2 3.6 4.2 5.5 ns t icky input reg ioclk pad to y 4.7 5.3 6.0 7.0 9.2 ns t ocky output reg ioclk pad to y 4.7 5.3 6.0 7.0 9.2 ns t iclry input asynchronous clear to y 4.7 5.3 6.0 7.0 9.2 ns t oclry output asynchronous clear to y 4.7 5.3 6.0 7.0 9.2 ns predicted input routing delays 2 t rd1 fo = 1 routing delay 0. 9 1.0 1.1 1.3 1.7 ns t rd2 fo = 2 routing delay 1.2 1.4 1.6 1.8 2.4 ns t rd3 fo = 3 routing delay 1. 4 1.6 1.8 2.1 2.8 ns t rd4 fo = 4 routing delay 1. 7 1.9 2.2 2.5 3.3 ns t rd8 fo = 8 routing delay 2.8 3.2 3.6 4.2 5.5 ns i/o module sequential timing (wrt ioclk pad) t inh input f-f data hold 0. 0 0.0 0.0 0.0 0.0 ns t insu input f-f data setup 1.8 1.7 2.0 2.3 2.3 ns t ideh input data enable hold 0.0 0.0 0.0 0.0 0.0 ns t idesu input data enable setup 5.8 6.5 7.5 8.6 8.6 ns t outh output f-f data hold 0.7 0.8 0.9 1.0 1.0 ns t outsu output f-f data setup 0.7 0.8 0.9 1.0 1.0 ns t odeh output data enable hold 0.3 0.4 0.4 0.5 0.5 ns f odesu output data enable setup 1.3 1.5 1.7 2.0 2.0 ns notes: 1. the ?2 and ?3 speed grades have been discontinued. refer to pdn 0104 , pdn 0203 , pdn 0604, and pdn 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn . 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment.
detailed specifications 2-32 revision 3 a1440a, a14v40a timing ch aracteristics (continued) table 2-28 ? a1440a, a14v40a worst-case commercial conditions, vcc = 4.75 v, t j = 70c i/o module ? ttl output timing 1 ?3 speed 2 ?2 speed 2 ?1 speed std. speed 3.3 v speed 1 units parameter/description min. max. min. max. min. m ax. min. max. min. max. t dhs data to pad, high slew 5.0 5.6 6.4 7.5 9.8 ns t dls data to pad, low slew 8.0 9.0 10.2 12.0 15.6 ns t enzhs enable to pad, z to h/l, high slew 4.0 4.5 5.1 6.0 7.8 ns t enzls enable to pad, z to h/l, low slew 7.4 8.3 9.4 11.0 14.3 ns t enhsz enable to pad, h/l to z, high slew 7.4 8.3 9.4 11.0 14.3 ns t enlsz enable to pad, h/l to z, low slew 7.4 8.3 9.4 11.0 14.3 ns t ckhs ioclk pad to pad h/l, high slew 8.5 8.5 9.5 11.0 14.3 ns t ckls ioclk pad to pad h/l, low slew 11.3 11.3 13.5 15.0 19.5 ns d tlhhs delta low to high, high slew 0.02 0.02 0.03 0.03 0.04 ns/pf d tlhls delta low to high, low slew 0.05 0.05 0.06 0.07 0.09 ns/pf d thlhs delta high to low, high slew 0.04 0.04 0.04 0.05 0.07 ns/pf d thlls delta high to low, low slew 0.05 0.05 0.06 0.07 0.09 ns/pf i/o module ? cmos output timing 1 t dhs data to pad, high slew 6.2 7.0 7.9 9.3 12.1 ns t dls data to pad, low slew 11.7 13.1 14.9 17.5 22.8 ns t enzhs enable to pad, z to h/l, high slew 5.2 5.9 6.6 7.8 10.1 ns t enzls enable to pad, z to h/l, low slew 8.9 10.0 11.3 13.3 17.3 ns t enhsz enable to pad, h/l to z, high slew 7.4 8.3 9.4 11.0 14.3 ns t enlsz enable to pad, h/l to z, low slew 7.4 8.3 9.4 11.0 14.3 ns t ckhs ioclk pad to pad h/l, high slew 9.0 9.0 10.1 11.8 14.3 ns t ckls ioclk pad to pad h/l, low slew 13.0 13.0 15.6 17.3 22.5 ns d tlhhs delta low to high, high slew 0.04 0.04 0.05 0.06 0.08 ns/pf d tlhls delta low to high, low slew 0.07 0.08 0.09 0.11 0.14 ns/pf d thlhs delta high to low, high slew 0.03 0.03 0.03 0.04 0.05 ns/pf d thlls delta high to low, low slew 0.04 0.04 0.04 0.05 0.07 ns/pf notes: 1. delays based on 35 pf loading. 2. the ?2 and ?3 speed grades have been discontinued. refer to pdn 0104 , pdn 0203 , pdn 0604, and pdn 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn .
accelerator series fpgas ? act 3 family revision 3 2-33 a1440a, a14v40a timing ch aracteristics (continued) table 2-29 ? a1440a, a14v40a worst-case commercial conditions, vcc = 4.75 v, t j = 70c dedicated (hardwired) i/o clock network ?3 speed 1 ?2 speed 1 ?1 speed std. speed 3.3 v speed 1 units parameter/description min. max. min. max. min. m ax. min. max. min. max. t iockh input low to high (pad to i/o module input) 2.0 2.3 2.6 3.0 3.5 ns t iopwh minimum pulse width high 1.9 2.4 3.3 3.8 4.8 ns t ipowl minimum pulse width low 1.9 2.4 3.3 3.8 4.8 ns t iosapw minimum asynchronous pulse width 1.9 2.4 3.3 3.8 4.8 ns t iocksw maximum skew 0.4 0.4 0.4 0.4 0.4 ns t iop minimum period 4.0 5.0 6.8 8.0 10.0 ns f iomax maximum frequency 250 200 150 125 100 mhz dedicated (hardwir ed) array clock t hckh input low to high (pad to s-module input) 3.0 3.4 3.9 4.5 5.5 ns t hckl input high to low (pad to s-module input) 3.0 3.4 3.9 4.5 5.5 ns t hpwh minimum pulse width high 1.9 2.4 3.3 3.8 4.8 ns t hpwl minimum pulse width low 1.9 2.4 3.3 3.8 4.8 ns t hcksw delta high to low, low slew 0.3 0.3 0.3 0.3 0.3 ns t hp minimum period 4.0 5.0 6.8 8.0 10.0 ns f hmax maximum frequency 250 200 150 125 100 mhz routed array clock networks t rckh input low to high (fo = 64) 3.7 4.1 4.7 5.5 9.0 ns t rckl input high to low (fo = 64) 4.0 4.5 5.1 6.0 9.0 ns t rpwh min. pulse width high (fo = 64) 3.3 3.8 4.2 4.9 6.5 ns t rpwl min. pulse width low (fo = 64) 3.3 3.8 4.2 4.9 6.5 ns t rcksw maximum skew (fo = 128) 0.7 0.8 0.9 1.0 1.0 ns t rp minimum period (fo = 64) 6.8 8.0 8.7 10.0 13.4 ns f rmax maximum frequency (fo = 64) 150 125 115 100 75 mhz clock-to-clock skews t iohcksw i/o clock to h-clock skew 0.0 1.7 0.0 1.8 0.0 2.0 0.0 2.2 0.0 3.0 ns t iorcksw i/o clock to r-clock skew (fo = 64) (fo = 144) 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 3.0 3.0 ns t hrcksw h-clock to r-clock skew (fo = 64) (fo = 144) 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 ns notes: 1. the ?2 and ?3 speed grades have been discontinued. refer to pdn 0104 , pdn 0203 , pdn 0604, and pdn 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn . 2. delays based on 35 pf loading.
detailed specifications 2-34 revision 3 a1460a, a14v60a ti ming characteristics table 2-30 ? a1460a, a14v60a worst-case commercial conditions, vcc = 4.75 v, t j = 70c 1 logic module propagation delays 2 ?3 speed 3 ?2 speed 3 ?1 speed std. speed 3.3 v speed 1 units parameter/description min. max. min. max. min. max. min. max. min. max. t pd internal array module 2.0 2.3 2.6 3.0 3.9 ns t co sequential clock to q 2.0 2.3 2.6 3.0 3.9 ns t clr asynchronous clear to q 2.0 2.3 2.6 3.0 3.9 ns predicted routing delays 4 t rd1 fo = 1 routing delay 0.9 1.0 1.1 1.3 1.7 ns t rd2 fo = 2 routing delay 1.2 1.4 1.6 1.8 2.4 ns t rd3 fo = 3 routing delay 1.4 1.6 1.8 2.1 2.8 ns t rd4 fo = 4 routing delay 1.7 1.9 2.2 2.5 3.3 ns t rd8 fo = 8 routing delay 2.8 3.2 3.6 4.2 5.5 ns logic module sequential timing t sud flip-flop data input setup 0.5 0.6 0.7 0.8 0.8 ns t hd flip-flop data input hold 0.0 0.0 0.0 0.0 0.0 ns t sud latch data input setup 0.5 0.6 0.7 0.8 0.8 ns t hd latch data input hold 0.0 0.0 0.0 0.0 0.0 ns t wasyn asynchronous pulse width 2.4 3.2 3.8 4.8 6.5 ns t wclka flip-flop clock pulse width 2.4 3.2 3.8 4.8 6.5 ns t a flip-flop clock input period 5.0 6.8 8.0 10.0 13.4 ns f max flip-flop clock frequency 200 150 125 100 75 mhz notes: 1. vcc = 3.0 v for 3.3 v specifications. 2. for dual-module macros, use t pd + t rd1 + t pdn + t co + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. 3. the ?2 and ?3 speed grades have been discontinued. refer to pdn 0104 , pdn 0203 , pdn 0604, and pdn 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn . 4. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual rout ing delay measurements performed on the device prior to shipment.
accelerator series fpgas ? act 3 family revision 3 2-35 a1460a, a14v60a timing ch aracteristics (continued) table 2-31 ? a1460a, a14v60a worst-case commercial conditions, vcc = 4.75 v, t j = 70c i/o module input propagation delays ?3 speed 1 ?2 speed 1 ?1 speed std. speed 3.3 v speed 1 units parameter/description min. max. min. max. min. m ax. min. max. min. max. t iny input data pad to y 2.8 3.2 3.6 4.2 5.5 ns t icky input reg ioclk pad to y 4.7 5.3 6.0 7.0 9.2 ns t ocky output reg ioclk pad to y 4.7 5.3 6.0 7.0 9.2 ns t iclry input asynchronous clear to y 4.7 5.3 6.0 7.0 9.2 ns t oclry output asynchronous clear to y 4.7 5.3 6.0 7.0 9.2 ns predicted input routing delays 2 t rd1 fo = 1 routing delay 0. 9 1.0 1.1 1.3 1.7 ns t rd2 fo = 2 routing delay 1.2 1.4 1.6 1.8 2.4 ns t rd3 fo = 3 routing delay 1. 4 1.6 1.8 2.1 2.8 ns t rd4 fo = 4 routing delay 1. 7 1.9 2.2 2.5 3.3 ns t rd8 fo = 8 routing delay 2.8 3.2 3.6 4.2 5.5 ns i/o module sequential timing (wrt ioclk pad) t inh input f-f data hold 0. 0 0.0 0.0 0.0 0.0 ns t insu input f-f data setup 1.3 1.5 1.8 2.0 2.0 ns t ideh input data enable hold 0.0 0.0 0.0 0.0 0.0 ns t idesu input data enable setup 5.8 6.5 7.5 8.6 8.6 ns t outh output f-f data hold 0.7 0.8 0.9 1.0 1.0 ns t outsu output f-f data setup 0.7 0.8 0.9 1.0 1.0 ns t odeh output data enable hold 0.3 0.4 0.4 0.5 0.5 ns f odesu output data enable setup 1.3 1.5 1.7 2.0 2.0 ns notes: 5. the ?2 and ?3 speed grades have been discontinued. refer to pdn 0104 , pdn 0203 , pdn 0604, and pdn 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn . 6. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment.
detailed specifications 2-36 revision 3 a1460a, a14v60a timing ch aracteristics (continued) table 2-32 ? a1460a, a14v60a worst-case commercial conditions, vcc = 4.75 v, t j = 70c i/o module ? ttl output timing 1 ?3 speed 2 ?2 speed 2 ?1 speed std. speed 3.3 v speed 1 units parameter/description min. max. min. max. min. m ax. min. max. min. max. t dhs data to pad, high slew 5.0 5.6 6.4 7.5 9.8 ns t dls data to pad, low slew 8.0 9.0 10.2 12.0 15.6 ns t enzhs enable to pad, z to h/l, high slew 4.0 4.5 5.1 6.0 7.8 ns t enzls enable to pad, z to h/l, low slew 7.4 8.3 9.4 11.0 14.3 ns t enhsz enable to pad, h/l to z, high slew 7.8 8.7 9.9 11.6 15.1 ns t enlsz enable to pad, h/l to z, low slew 7.4 8.3 9.4 11.0 14.3 ns t ckhs ioclk pad to pad h/l, high slew 9.0 9.0 10.0 11.5 15.0 ns t ckls ioclk pad to pad h/l, low slew 12.8 12.8 15.3 17.0 22.1 ns d tlhhs delta low to high, high slew 0.02 0.02 0.03 0.03 0.04 ns/pf d tlhls delta low to high, low slew 0.05 0.05 0.06 0.07 0.09 ns/pf d thlhs delta high to low, high slew 0.04 0.04 0.04 0.05 0.07 ns/pf d thlls delta high to low, low slew 0.05 0.05 0.06 0.07 0.09 ns/pf i/o module ? cmos output timing 1 t dhs data to pad, high slew 6.2 7.0 7.9 9.3 12.1 ns t dls data to pad, low slew 11.7 13.1 14.9 17.5 22.8 ns t enzhs enable to pad, z to h/l, high slew 5.2 5.9 6.6 7.8 10.1 ns t enzls enable to pad, z to h/l, low slew 8.9 10.0 11.3 13.3 17.3 ns t enhsz enable to pad, h/l to z, high slew 7.4 8.3 9.4 11.0 14.3 ns t enlsz enable to pad, h/l to z, low slew 7.4 8.3 9.4 11.0 14.3 ns t ckhs ioclk pad to pad h/l, high slew 10.4 10.4 12.1 13.8 17.9 ns t ckls ioclk pad to pad h/l, low slew 14.5 14.5 17.4 19.3 25.1 ns d tlhhs delta low to high, high slew 0.04 0.04 0.05 0.06 0.08 ns/pf d tlhls delta low to high, low slew 0.07 0.08 0.09 0.11 0.14 ns/pf d thlhs delta high to low, high slew 0.03 0.03 0.03 0.04 0.05 ns/pf d thlls delta high to low, low slew 0.04 0.04 0.04 0.05 0.07 ns/pf notes: 1. delays based on 35 pf loading. 2. the ?2 and ?3 speed grades have been discontinued. refer to pdn 0104 , pdn 0203 , pdn 0604, and pdn 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn .
accelerator series fpgas ? act 3 family revision 3 2-37 a1460a, a14v60a timing ch aracteristics (continued) table 2-33 ? a1460a, a14v60a worst-case commercial conditions, vcc = 4.75 v, t j = 70c dedicated (hardwired) i/o clock network ?3 speed 1 ?2 speed 1 ?1 speed std. speed 3.3 v speed 1 units parameter/description min. max. min. max. min. m ax. min. max. min. max. t iockh input low to high (pad to i/o module input) 2.3 2.6 3.0 3.5 4.5 ns t iopwh minimum pulse width high 2.4 3.2 3.8 4.8 6.5 ns t ipowl minimum pulse width low 2.4 3.2 3.8 4.8 6.5 ns t iosapw minimum asynchronous pulse width 2.4 3.2 3.8 4.8 6.5 ns t iocksw maximum skew 0.6 0.6 0.6 0.6 0.6 ns t iop minimum period 5.0 6.8 8.0 10.0 13.4 ns f iomax maximum frequency 200 150 125 100 75 mhz dedicated (hardwir ed) array clock t hckh input low to high (pad to s-module input) 3.7 4.1 4.7 5.5 7.0 ns t hckl input high to low (pad to s-module input) 3.7 4.1 4.7 5.5 7.0 ns t hpwh minimum pulse width high 2.4 3.2 3.8 4.8 6.5 ns t hpwl minimum pulse width low 2.4 3.2 3.8 4.8 6.5 ns t hcksw delta high to low, low slew 0.6 0.6 0.6 0.6 0.6 ns t hp minimum period 5.0 6.8 8.0 10.0 13.4 ns f hmax maximum frequency 200 150 125 100 75 mhz routed array clock networks t rckh input low to high (fo = 64) 6.0 6.8 7.7 9.0 11.8 ns t rckl input high to low (fo = 64) 6.0 6.8 7.7 9.0 11.8 ns t rpwh min. pulse width high (fo = 64) 4.1 4.5 5.4 6.1 8.2 ns t rpwl min. pulse width low (fo = 64) 4.1 4.5 5.4 6.1 8.2 ns t rcksw maximum skew (fo = 128) 1.2 1.4 1.6 1.8 1.8 ns t rp minimum period (fo = 64) 8.3 9.3 11.1 12.5 16.7 ns f rmax maximum frequency (fo = 64) 120 105 90 80 60 mhz clock-to-clock skews t iohcksw i/o clock to h-clock skew 0.0 2.6 0.0 2.7 0.0 2.9 0.0 3.0 0.0 3.0 ns t iorcksw i/o clock to r-clock skew (fo = 64) (fo = 216) 0.0 0.0 1.7 5.0 0.0 0.0 1.7 5.0 0.0 0.0 1.7 5.0 0.0 0.0 1.7 5.0 0.0 0.0 5.0 5.0 ns t hrcksw h-clock to r-clock skew (fo = 64) (fo = 216) 0.0 0.0 1.3 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 ns notes: 1. the ?2 and ?3 speed grades have been discontinued. refer to pdn 0104 , pdn 0203 , pdn 0604, and pdn 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn . 2. delays based on 35 pf loading.
detailed specifications 2-38 revision 3 a14100a, a14v100a ti ming characteristics table 2-34 ? a14100a, a14v100a worst-case commercial conditions, vcc = 4.75 v, t j = 70c 1 logic module propagation delays 2 ?3 speed 3 ?2 speed 3 ?1 speed std. speed 3.3 v speed 1 units parameter/description min. max. min. max. min. max. min. max. min. max. t pd internal array module 2.0 2.3 2.6 3.0 3.9 ns t co sequential clock to q 2.0 2.3 2.6 3.0 3.9 ns t clr asynchronous clear to q 2.0 2.3 2.6 3.0 3.9 ns predicted routing delays 4 t rd1 fo = 1 routing delay 0.9 1.0 1.1 1.3 1.7 ns t rd2 fo = 2 routing delay 1.2 1.4 1.6 1.8 2.4 ns t rd3 fo = 3 routing delay 1.4 1.6 1.8 2.1 2.8 ns t rd4 fo = 4 routing delay 1.7 1.9 2.2 2.5 3.3 ns t rd8 fo = 8 routing delay 2.8 3.2 3.6 4.2 5.5 ns logic module sequential timing t sud flip-flop data input setup 0.5 0.6 0.8 0.8 0.8 ns t hd flip-flop data input hold 0.0 0.0 0.5 0.5 0.5 ns t sud latch data input setup 0.5 0.6 0.8 0.8 0.8 ns t hd latch data input hold 0.0 0.0 0.5 0.5 0.5 ns t wasyn asynchronous pulse width 2.4 3.2 3.8 4.8 6.5 ns t wclka flip-flop clock pulse width 2.4 3.2 3.8 4.8 6.5 ns t a flip-flop clock input period 5.0 6.8 8.0 10.0 13.4 ns f max flip-flop clock frequency 200 150 125 100 75 mhz notes: 1. vcc = 3.0 v for 3.3 v specifications. 2. for dual-module macros, use t pd + t rd1 + t pdn + t co + t rd1 + t pdn or t pd1 + t rd1 + t sud , whichever is appropriate. 3. the ?2 and ?3 speed grades have been discontinued. refer to pdn 0104 , pdn 0203 , pdn 0604, and pdn 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn . 4. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual rout ing delay measurements performed on the device prior to shipment.
accelerator series fpgas ? act 3 family revision 3 2-39 a14100a, a14v100a timing ch aracteristics (continued) table 2-35 ? a14100a, a14v100a worst-case commercial conditions, vcc = 4.75 v, t j = 70c i/o module input propagation delays ?3 speed 1 ?2 speed 1 ?1 speed std. speed 3.3 v speed 1 units parameter/description min. max. min. max. min. m ax. min. max. min. max. t iny input data pad to y 2.8 3.2 3.6 4.2 5.5 ns t icky input reg ioclk pad to y 4.7 5.3 6.0 7.0 9.2 ns t ocky output reg ioclk pad to y 4.7 5.3 6.0 7.0 9.2 ns t iclry input asynchronous clear to y 4.7 5.3 6.0 7.0 9.2 ns t oclry output asynchronous clear to y 4.7 5.3 6.0 7.0 9.2 ns predicted input routing delays 2 t rd1 fo = 1 routing delay 0. 9 1.0 1.1 1.3 1.7 ns t rd2 fo = 2 routing delay 1.2 1.4 1.6 1.8 2.4 ns t rd3 fo = 3 routing delay 1. 4 1.6 1.8 2.1 2.8 ns t rd4 fo = 4 routing delay 1. 7 1.9 2.2 2.5 3.3 ns t rd8 fo = 8 routing delay 2.8 3.2 3.6 4.2 5.5 ns i/o module sequential timing (wrt ioclk pad) t inh input f-f data hold 0. 0 0.0 0.0 0.0 0.0 ns t insu input f-f data setup 1.2 1.4 1.5 1.8 1.8 ns t ideh input data enable hold 0.0 0.0 0.0 0.0 0.0 ns t idesu input data enable setup 5.8 6.5 7.5 8.6 8.6 ns t outh output f-f data hold 0.7 0.8 1.0 1.0 1.0 ns t outsu output f-f data setup 0.7 0.8 1.0 1.0 1.0 ns t odeh output data enable hold 0.3 0.4 0.5 0.5 0.5 ns f odesu output data enable setup 1.3 1.5 2.0 2.0 2.0 ns notes: * 1. the ?2 and ?3 speed grades have been discontinued. refer to pdn 0104 , pdn 0203 , pdn 0604, and pdn 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn . 2. routing delays are for typical designs across worst-case operating conditions. these parameters should be used for estimating device performance. post-route timing analysis or simulation is required to determine actual worst-case performance. post-route timing is based on actual routing delay measurements performed on the device prior to shipment.
detailed specifications 2-40 revision 3 a14100a, a14v100a timing ch aracteristics (continued) table 2-36 ? a14100a, a14v100a worst-case commercial conditions, vcc = 4.75 v, t j = 70c i/o module ? ttl output timing 1 ?3 speed 2 ?2 speed 2 ?1 speed std. speed 3.3 v speed 1 units parameter/description min. max. min. max. min. m ax. min. max. min. max. t dhs data to pad, high slew 5.0 5.6 6.4 7.5 9.8 ns t dls data to pad, low slew 8.0 9.0 10.2 12.0 15.6 ns t enzhs enable to pad, z to h/l, high slew 4.0 4.5 5.1 6.0 7.8 ns t enzls enable to pad, z to h/l, low slew 7.4 8.3 9.4 11.0 14.3 ns t enhsz enable to pad, h/l to z, high slew 8.0 9.0 10.2 12.0 15.6 ns t enlsz enable to pad, h/l to z, low slew 7.4 8.3 9.4 11.0 14.3 ns t ckhs ioclk pad to pad h/l, high slew 9.5 9.5 10.5 12.0 15.6 ns t ckls ioclk pad to pad h/l, low slew 12.8 12.8 15.3 17.0 22.1 ns d tlhhs delta low to high, high slew 0.02 0.02 0.03 0.03 0.04 ns/pf d tlhls delta low to high, low slew 0.05 0.05 0.06 0.07 0.09 ns/pf d thlhs delta high to low, high slew 0.04 0.04 0.04 0.05 0.07 ns/pf d thlls delta high to low, low slew 0.05 0.05 0.06 0.07 0.09 ns/pf i/o module ? cmos output timing 1 t dhs data to pad, high slew 6.2 7.0 7.9 9.3 12.1 ns t dls data to pad, low slew 11.7 13.1 14.9 17.5 22.8 ns t enzhs enable to pad, z to h/l, high slew 5.2 5.9 6.6 7.8 10.1 ns t enzls enable to pad, z to h/l, low slew 8.9 10.0 11.3 13.3 17.3 ns t enhsz enable to pad, h/l to z, high slew 8.0 9.0 10.0 12.0 15.6 ns t enlsz enable to pad, h/l to z, low slew 7.4 8.3 9.4 11.0 14.3 ns t ckhs ioclk pad to pad h/l, high slew 10.4 10.4 12.4 13.8 17.9 ns t ckls ioclk pad to pad h/l, low slew 14.5 14.5 17.4 19.3 25.1 ns d tlhhs delta low to high, high slew 0.04 0.04 0.05 0.06 0.08 ns/pf d tlhls delta low to high, low slew 0.07 0.08 0.09 0.11 0.14 ns/pf d thlhs delta high to low, high slew 0.03 0.03 0.03 0.04 0.05 ns/pf d thlls delta high to low, low slew 0.04 0.04 0.04 0.05 0.07 ns/pf notes: * 1. delays based on 35 pf loading. 2. the ?2 and ?3 speed grades have been discontinued. refer to pdn 0104 , pdn 0203 , pdn 0604, and pdn 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn .
accelerator series fpgas ? act 3 family revision 3 2-41 a14100a, a14v100a timing ch aracteristics (continued) table 2-37 ? a14100a, a14v100a worst-case commercial conditions, vcc = 4.75 v, t j = 70c dedicated (hardwired) i/o clock network ?3 speed 1 ?2 speed 1 ?1 speed std. speed 3.3 v speed 1 units parameter/description min. max. min. max. min. m ax. min. max. min. max. t iockh input low to high (pad to i/o module input) 2.3 2.6 3.0 3.5 4.5 ns t iopwh minimum pulse width high 2.4 3.3 3.8 4.8 6.5 ns t ipowl minimum pulse width low 2.4 3.3 3.8 4.8 6.5 ns t iosapw minimum asynchronous pulse width 2.4 3.3 3.8 4.8 6.5 ns t iocksw maximum skew 0.6 0.6 0.7 0.8 0.6 ns t iop minimum period 5.0 6.8 8.0 10.0 13.4 ns f iomax maximum frequency 200 150 125 100 75 mhz dedicated (hardwir ed) array clock t hckh input low to high (pad to s-module input) 3.7 4.1 4.7 5.5 7.0 ns t hckl input high to low (pad to s-module input) 3.7 4.1 4.7 5.5 7.0 ns t hpwh minimum pulse width high 2.4 3.3 3.8 4.8 6.5 ns t hpwl minimum pulse width low 2.4 3.3 3.8 4.8 6.5 ns t hcksw delta high to low, low slew 0.6 0.6 0.7 0.8 0.6 ns t hp minimum period 5.0 6.8 8.0 10.0 13.4 ns f hmax maximum frequency 200 150 125 100 75 mhz routed array clock networks t rckh input low to high (fo = 64) 6.0 6.8 7.7 9.0 11.8 ns t rckl input high to low (fo = 64) 6.0 6.8 7.7 9.0 11.8 ns t rpwh min. pulse width high (fo = 64) 4.1 4.5 5.4 6.1 8.2 ns t rpwl min. pulse width low (fo = 64) 4.1 4.5 5.4 6.1 8.2 ns t rcksw maximum skew (fo = 128) 1.2 1.4 1.6 1.8 1.8 ns t rp minimum period (fo = 64) 8.3 9.3 11.1 12.5 16.7 ns f rmax maximum frequency (fo = 64) 120 105 90 80 60 mhz clock-to-clock skews t iohcksw i/o clock to h-clock skew 0.0 2.6 0.0 2.7 0.0 2.9 0.0 3.0 0.0 3.0 ns t iorcksw i/o clock to r-clock skew (fo = 64) (fo = 350) 0.0 0.0 1.7 5.0 0.0 0.0 1.7 5.0 0.0 0.0 1.7 5.0 0.0 0.0 1.7 5.0 0.0 0.0 5.0 5.0 ns t hrcksw h-clock to r-clock skew (fo = 64) (fo = 350) 0.0 0.0 1.3 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 0.0 0.0 1.0 3.0 ns notes: * 1. the ?2 and ?3 speed grades have been discontinued. refer to pdn 0104 , pdn 0203 , pdn 0604, and pdn 1004 at http://www.microsemi.com/soc/support/notifications/default.aspx#pdn . 2. delays based on 35 pf loading.
detailed specifications 2-42 revision 3 pin descriptions clka clock a (input) clock input for clock distribution networks. the clock input is buffered prior to clocking the logic modules. this pin can also be used as an i/o. clkb clock b (input) clock input for clock distribution networks. the clock input is buffered prior to clocking the logic modules. this pin can also be used as an i/o. gnd ground low supply voltage. hclk dedicated (hard-wired) array clock (input) clock input for sequential modules. th is input is directly wired to each s-module and offers clock speeds independent of the number of s-modules being dr iven. this pin can also be used as an i/o. i/o input/output (input, output) the i/o pin functions as an input, ou tput, three-state, or bi directional buffer. input and output levels are compatible with standard ttl and cm os specifications. un used i/o pins are tristated by the designer series software. ioclk dedicated (hard-wired) i/o clock (input) clock input for i/o modules. this input is directly wired to each i/o module and offers clock speeds independent of the number of i/o modules being driven. this pin can also be used as an i/o. iopcl dedicated (hard-wired) i/o preset/clear (input) input for i/o preset or clear. this global input is di rectly wired to the preset and clear inputs of all i/o registers. this pin functions as an i/o wh en no i/o preset or clear macros are used. mode mode (input) the mode pin controls the use of diagnostic pins (dclk, pra, prb, sdi). when the mode pin is high, the special functions are acti ve. when the mode pin is low, the pins function as i/os. to provide actionprobe capability, the mode pin should be termi nated to gnd through a 10k resistor so that the mode pin can be pulled high when required. nc no connection this pin is not connected to circuitry within the device. pra probe a (output) the probe a pin is used to output data from an y user-defined design node within the device. this independent diagnostic pin can be used in conjunction with the probe b pin to allow real-time diagnostic output of any signal path within the device. the probe a pin can be used as a user-defined i/o when debugging has been completed. the pin?s probe capabilities can be permanently disabled to protect programmed design confidentiality. pra is accessibl e when the mode pin is high. this pin functions as an i/o when the mode pin is low. prb probe b (output) the probe b pin is used to output data from an y user-defined design node within the device. this independent diagnostic pin can be used in conjunction with the probe a pin to allow real-time diagnostic output of any signal path within the device. the probe b pin can be used as a user-defined i/o when debugging has been completed. the pin?s probe capabilities can be permanently disabled to protect programmed design confidentiality. prb is accessibl e when the mode pin is high. this pin functions as an i/o when the mode pin is low. sdi serial data input (input) serial data input for diagnostic probe and device programming. sdi is active when the mode pin is high. this pin functions as an i/o when the mode pin is low.
accelerator series fpgas ? act 3 family revision 3 2-43 sdo serial data output (output) serial data output for diagnostic probe. sdo is acti ve when the mode pin is hi gh. this pin functions as an i/o when the mode pin is low. dclk diagnostic clock (input) clock input for diagnostic probe and device programming. dclk is active when the mode pin is high. this pin functions as an i/o when the mode pin is low. vcc 5 v supply voltage high supply voltage.

revision 3 3-1 3 ? package pin assignments pl84 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx . note: this is the top view of the package. 12 13 14 15 16 18 17 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 68 69 67 66 65 64 63 62 61 60 59 58 57 56 55 54 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 1110 9 8 7 6 5 4 3 2 1 84838281807978777675 84-pin plcc
package pin assignments 3-2 revision 3 notes: 1. all unlisted pin num bers are user i/os. 2. nc denotes no connection. 3. mode should be terminated to gnd through a 10k resist or to enable actionprobe us age; otherwise it can be terminated directly to gnd. pl84 pin number a1415, a14v15 function a1425, a14v25 function a1440, a14v40 function 1 vcc vcc vcc 2 gnd gnd gnd 3 vcc vcc vcc 4 pra, i/o pra, i/o pra, i/o 11 dclk, i/o dclk, i/o dclk, i/o 12 sdi, i/o sdi, i/o sdi, i/o 16 mode mode mode 27 gnd gnd gnd 28 vcc vcc vcc 40 prb, i/o prb, i/o prb, i/o 41 vcc vcc vcc 42 gnd gnd gnd 43 vcc vcc vcc 45 hclk, i/o hclk, i/o hclk, i/o 52 sdo sdo sdo 53 iopcl, i/o iopcl, i/o iopcl, i/o 59 vcc vcc vcc 60 vcc vcc vcc 61 gnd gnd gnd 68 vcc vcc vcc 69 gnd gnd gnd 74 ioclk, i/o ioclk, i/o ioclk, i/o 83 clka, i/o clka, i/o clka, i/o 84 clkb, i/o clkb, i/o clkb, i/o
accelerator series fpgas ? act 3 family revision 3 3-3 pq100 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx note: this is the top view of the package. 100-pin pqfp 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 123456789101112131415161718192021222324252627282930
package pin assignments 3-4 revision 3 notes: 1. all unlisted pin num bers are user i/os. 2. nc denotes no connection. 3. mode should be terminated to gnd through a 10k resist or to enable actionprobe us age; otherwise it can be terminated directly to gnd. pq100 pin number a1415 function a1425 function 2 ioclk, i/o ioclk, i/o 14 clka, i/o clka, i/o 15 clkb, i/o clkb, i/o 16 vcc vcc 17 gnd gnd 18 vcc vcc 19 gnd gnd 20 pra, i/o pra, i/o 27 dclk, i/o dclk, i/o 28 gnd gnd 29 sdi, i/o sdi, i/o 34 mode mode 35 vcc vcc 36 gnd gnd 47 gnd gnd 48 vcc vcc 61 prb, i/o prb, i/o 62 gnd gnd 63 vcc vcc 64 gnd gnd 65 vcc vcc 67 hclk, i/o hclk, i/o 77 sdo sdo 78 iopcl, i/o iopcl, i/o 79 gnd gnd 85 vcc vcc 86 vcc vcc 87 gnd gnd 96 vcc vcc 97 gnd gnd
accelerator series fpgas ? act 3 family revision 3 3-5 pq160 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx note: this is the top view of the package 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 160-pin pqfp
package pin assignments 3-6 revision 3 pq160 pin number a1425, a14v25 function a1440, a14v40 function a1460, a14v60 function 1 gnd gnd gnd 2 sdi, i/o sdi, i/o sdi, i/o 5 nc i/o i/o 9 mode mode mode 10 vcc vcc vcc 14 nc i/o i/o 15 gnd gnd gnd 18 vcc vcc vcc 19 gnd gnd gnd 20 nc i/o i/o 24 nc i/o i/o 27 nc i/o i/o 28 vcc vcc vcc 29 vcc vcc vcc 40 gnd gnd gnd 41 nc i/o i/o 43 nc i/o i/o 45 nc i/o i/o 46 vcc vcc vcc 47 nc i/o i/o 49 nc i/o i/o 51 nc i/o i/o 53 nc i/o i/o 58 prb, i/o prb, i/o prb, i/o 59 gnd gnd gnd 60 vcc vcc vcc 62 hclk, i/o hclk, i/o hclk, i/o 63 gnd gnd gnd 74 nc i/o i/o 75 vcc vcc vcc 76 nc i/o i/o 77 nc i/o i/o 78 nc i/o i/o 79 sdo sdo sdo 80 iopcl, i/o iopcl, i/o iopcl, i/o 81 gnd gnd gnd 90 vcc vcc vcc 91 vcc vcc vcc
accelerator series fpgas ? act 3 family revision 3 3-7 notes: 1. all unlisted pin num bers are user i/os. 2. nc denotes no connection. 3. mode should be terminated to gnd through a 10k resist or to enable actionprobe us age; otherwise it can be terminated directly to gnd. 92 nc i/o i/o 93 nc i/o i/o 98 gnd gnd gnd 99 vcc vcc vcc 100 nc i/o i/o 103 gnd gnd gnd 107 nc i/o i/o 109 nc i/o i/o 110 vcc vcc vcc 111 gnd gnd gnd 112 vcc vcc vcc 113 nc i/o i/o 119 nc i/o i/o 120 ioclk, i/o ioclk, i/o ioclk, i/o 121 gnd gnd gnd 124 nc i/o i/o 127 nc i/o i/o 136 clka, i/o clka, i/o clka, i/o 137 clkb, i/o clkb, i/o clkb, i/o 138 vcc vcc vcc 139 gnd gnd gnd 140 vcc vcc vcc 141 gnd gnd gnd 142 pra, i/o pra, i/o pra, i/o 143 nc i/o i/o 145 nc i/o i/o 147 nc i/o i/o 149 nc i/o i/o 151 nc i/o i/o 153 nc i/o i/o 154 vcc vcc vcc 160 dclk, i/o dclk, i/o dclk, i/o pq160 pin number a1425, a14v25 function a1440, a14v40 function a1460, a14v60 function
package pin assignments 3-8 revision 3 pq208, rq208 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx note: this is the top view of the package 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 168 93 167 94 166 95 165 96 164 97 163 98 162 99 161 100 160 101 159 102 158 103 157 104 116 41 115 42 114 43 113 44 112 45 111 46 110 47 109 48 108 49 107 50 106 51 105 52 208-pin pqfp, rqfp
accelerator series fpgas ? act 3 family revision 3 3-9 notes: 1. all unlisted pin num bers are user i/os. 2. nc denotes no connection. 3. mode should be terminated to gnd through a 10k resist or to enable actionprobe us age; otherwise it can be terminated directly to gnd. pq208, rq208 pin number a1460, a14v60 function a14100, a14v100 function 1gnd gnd 2 sdi, i/o sdi, i/o 11 mode mode 12 vcc vcc 25 vcc vcc 26 gnd gnd 27 vcc vcc 28 gnd gnd 40 vcc vcc 41 vcc vcc 52 gnd gnd 53 nc i/o 60 vcc vcc 65 nc i/o 76 prb, i/o prb, i/o 77 gnd gnd 78 vcc vcc 79 gnd gnd 80 vcc vcc 82 hclk, i/o hclk, i/o 98 vcc vcc 102 nc i/o 103 sdo sdo 104 iopcl, i/o iopcl, i/o 105 gnd gnd 114 vcc vcc 115 vcc vcc 116 nc i/o 129 gnd gnd 130 vcc vcc 131 gnd gnd 132 vcc vcc 145 vcc vcc 146 gnd gnd 147 nc i/o 148 vcc vcc 156 ioclk, i/o ioclk, i/o 157 gnd gnd 158 nc i/o 164 vcc vcc 180 clka, i/o clka, i/o 181 clkb, i/o clkb, i/o 182 vcc vcc 183 gnd gnd 184 vcc vcc 185 gnd gnd 186 pra, i/o pra, i/o 195 nc i/o 201 vcc vcc 205 nc i/o 208 dclk, i/o dclk, i/o pq208, rq208 pin number a1460, a14v60 function a14100, a14v100 function
package pin assignments 3-10 revision 3 tq176 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx note: this is the top view. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 41 42 43 44 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 140 139 138 137 176-pin tqfp 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 136 135 134 133
accelerator series fpgas ? act 3 family revision 3 3-11 notes: 1. all unlisted pin num bers are user i/os. 2. nc denotes no connection. 3. mode should be terminated to gnd through a 10k resist or to enable actionprobe us age; otherwise it can be terminated directly to gnd. tq176 pin number a1440, a14v40 function a1460, a14v60 function 1gnd gnd 2 sdi, i/o sdi, i/o 10 mode mode 11 vcc vcc 20 nc i/o 21 gnd gnd 22 vcc vcc 23 gnd gnd 32 vcc vcc 33 vcc vcc 44 gnd gnd 49 nc i/o 51 nc i/o 63 nc i/o 64 prb, i/o prb, i/o 65 gnd gnd 66 vcc vcc 67 vcc vcc 69 hclk, i/o hclk, i/o 82 nc i/o 83 nc i/o 87 sdo sdo 88 iopcl, i/o iopcl, i/o 89 gnd gnd 98 vcc vcc 99 vcc vcc 108 gnd gnd 109 vcc vcc 110 gnd gnd 119 nc i/o 121 nc i/o 122 vcc vcc 123 gnd gnd 124 vcc vcc 132 ioclk, i/o ioclk, i/o 133 gnd gnd 138 nc i/o 152 clka, i/o clka, i/o 153 clkb, i/o clkb, i/o 154 vcc vcc 155 gnd gnd 156 vcc vcc 157 pra, i/o pra, i/o 158 nc i/o 170 nc i/o 176 dclk, i/o dclk, i/o tq176 pin number a1440, a14v40 function a1460, a14v60 function
package pin assignments 3-12 revision 3 vq100 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx note: this is the top view. 1 2 3 4 5 7 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100-pin vqfp 75 74 73 72 71 69 70 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 32 31 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 94 95 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
accelerator series fpgas ? act 3 family revision 3 3-13 notes: 1. all unlisted pin num bers are user i/os. 2. nc denotes no connection. 3. mode should be terminated to gnd through a 10k resist or to enable actionprobe us age; otherwise it can be terminated directly to gnd. vq100 pin number a1415, a14v15 function a1425, a14v25 function a1440, a14v40 function 1 gnd gnd gnd 2 sdi, i/o sdi, i/o sdi, i/o 7 mode mode mode 8 vcc vcc vcc 9 gnd gnd gnd 20 vcc vcc vcc 21 nc i/o i/o 34 prb, i/o prb, i/o prb, i/o 35 vcc vcc vcc 36 gnd gnd gnd 37 vcc vcc vcc 39 hclk, i/o hclk, i/o hclk, i/o 49 sdo sdo sdo 50 iopcl, i/o iopcl, i/o iopcl, i/o 51 gnd gnd gnd 57 vcc vcc vcc 58 vcc vcc vcc 67 vcc vcc vcc 68 gnd gnd gnd 69 gnd gnd gnd 74 nc i/o i/o 75 ioclk, i/o ioclk, i/o ioclk, i/o 87 clka, i/o clka, i/o clka, i/o 88 clkb, i/o clkb, i/o clkb, i/o 89 vcc vcc vcc 90 vcc vcc vcc 91 gnd gnd gnd 92 pra, i/o pra, i/o pra, i/o 93 nc i/o i/o 100 dclk, i/o dclk, i/o dclk, i/o
package pin assignments 3-14 revision 3 cq132 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx note: this is the top view 132-pin cqfp pin #1 index 132 131 130 129 128 127 126 125 124 107 106 105 104 103 102 101 100 34 35 36 37 38 39 40 41 42 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 92 93 94 95 96 97 98 99 33 32 31 30 29 28 27 26 25 8 7 6 5 4 3 2 1
accelerator series fpgas ? act 3 family revision 3 3-15 notes: 1. all unlisted pin num bers are user i/os. 2. nc denotes no connection. 3. mode should be terminated to gnd through a 10k resist or to enable actionprobe us age; otherwise it can be terminated directly to gnd. cq132 pin number a1425 function 1nc 2gnd 3sdi, i/o 9mode 10 gnd 11 vcc 22 vcc 26 gnd 27 vcc 34 nc 36 gnd 42 gnd 43 vcc 48 prb, i/o 50 hclk, i/o 58 gnd 59 vcc 63 sdo 64 iopcl, i/o 65 gnd 66 nc 67 nc 74 gnd 75 vcc 78 vcc 89 vcc 90 gnd 91 vcc 92 gnd 98 ioclk, i/o 99 nc 100 nc 101 gnd 106 gnd 107 vcc 116 clka, i/o 117 clkb, i/o 118 pra, i/o 122 gnd 123 vcc 131 dclk, i/o 132 nc cq132 pin number a1425 function
package pin assignments 3-16 revision 3 cq196 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx note: this is the top view. 196-pin cqfp pin #1 index 196 195 194 193 192 191 190 189 188 155 154 153 152 151 150 149 148 50 51 52 53 54 55 56 57 58 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 140 141 142 143 144 145 146 147 49 48 47 46 45 44 43 42 41 8 7 6 5 4 3 2 1
accelerator series fpgas ? act 3 family revision 3 3-17 notes: 1. all unlisted pin num bers are user i/os. 2. nc denotes no connection. 3. mode should be terminated to gnd through a 10k resist or to enable actionprobe us age; otherwise it can be terminated directly to gnd. cq196 pin number a1460 function 1gnd 2sdi, i/o 11 mode 12 vcc 13 gnd 37 gnd 38 vcc 39 vcc 51 gnd 52 gnd 59 vcc 64 gnd 77 hclk, i/o 79 prb, i/o 86 gnd 94 vcc 98 gnd 99 sdo 100 iopcl, i/o 101 gnd 110 vcc 111 vcc 112 gnd 137 vcc 138 gnd 139 gnd 140 vcc 148 ioclk, i/o 149 gnd 155 vcc 162 gnd 172 clka, i/o 173 clkb, i/o 174 pra, i/o 183 gnd 189 vcc 193 gnd 196 dclk, i/o cq196 pin number a1460 function
package pin assignments 3-18 revision 3 cq256 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx note: this is the top view. 256-pin cqfp pin #1 index 256 255 254 253 252 251 250 249 248 200 199 198 197 196 195 194 193 65 66 67 68 69 70 71 72 73 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 185 186 187 188 189 190 191 192 64 63 62 61 60 59 58 57 56 8 7 6 5 4 3 2 1
accelerator series fpgas ? act 3 family revision 3 3-19 notes: 1. all unlisted pin num bers are user i/os. 2. nc denotes no connection. 3. mode should be terminated to gnd through a 10k resist or to enable actionprobe us age; otherwise it can be terminated directly to gnd. cq256 pin number a14100 function 1gnd 2sdi, i/o 11 mode 28 vcc 29 gnd 30 vcc 31 gnd 46 vcc 59 gnd 90 prb, i/o 91 gnd 92 vcc 93 gnd 94 vcc 96 hclk, i/o 110 gnd 126 sdo 127 iopcl, i/o 128 gnd 141 vcc 158 gnd 159 vcc 160 gnd 161 vcc 174 vcc 175 gnd 176 gnd 188 ioclk, i/o 189 gnd 219 clka, i/o 220 clkb, i/o 221 vcc 222 gnd 223 vcc 224 gnd 225 pra, i/o 240 gnd 256 dclk, i/o cq256 pin number a14100 function
package pin assignments 3-20 revision 3 bg225 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx note: this is the top view. a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
accelerator series fpgas ? act 3 family revision 3 3-21 notes: 1. all unlisted pin num bers are user i/os. 2. nc denotes no connection. 3. mode should be terminated to gnd through a 10k resist or to enable actionprobe us age; otherwise it can be terminated directly to gnd. 4. the bg225 package has been discontinued. bg225 a1460 function location clka or i/o c8 clkb or i/o b8 dclk or i/o b2 gnd a1, a15, d15, f8, g7, g8, g9, h6, h7, h8, h9, h10, j7, j8, j9, k8, p2, r15 hclk or i/o p9 ioclk or i/o b14 iopcl or i/o p14 mode d1 nc a11, b5, b7, d8, d12, f6, f11, h1, h12, h1 4, k11, l1, l13, n8, p5, r1, r8, r11, r14 pra or i/o a7 prb or i/o l7 sdi or i/o d4 sdo n13 vcc a8, b12, d5, d14, e3, e8, e13, h2, h3, h11, h15, k4, l2, l12, m8, m15, p4, p8, r13
package pin assignments 3-22 revision 3 bg313 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx note: this is the top view. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
accelerator series fpgas ? act 3 family revision 3 3-23 notes: 1. all unlisted pin num bers are user i/os. 2. nc denotes no connection. 3. mode should be terminated to gnd through a 10k resist or to enable actionprobe us age; otherwise it can be terminated directly to gnd. bg313 a14100, a14v100 function location clka or i/o j13 clkb or i/o g13 dclk or i/o b2 gnd a1, a25, ad2, ae25, j21, l13, m12, m14, n11, n13, n15, p12, p14, r13 hclk or i/o t14 ioclk or i/o b24 iopcl or i/o ad24 mode g3 nc a3, a13, a23, aa5, aa9, aa2 3, ab2, ab4, ab20, ac13, ac25, ad22, ae1, ae21, b14, c5, c25, d4, d24, e3, e21, f6, f10, f16, g1, g25, h18, h24, j1, j7 , j25, k12, l15, l17, m6, n1, n5, n7, n21, n23, p20, r11, t6, t8 , u9, u13, u21, v16, w7, y20, y24 pra or i/o h12 prb or i/o ad12 sdi or i/o c1 sdo ae23 vcc ab18, ad6, ae13, c13, c19, e13, g9, h22, k8, k20, m16, n3, n9, n25, u5, w13, v2, v22, v24
package pin assignments 3-24 revision 3 pg100 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx note: this is the top view. 1 a 234567891011 b c d e f g h j k l a b c d e f g h j k l 100-pin cpga 1234567891011 orientation pin
accelerator series fpgas ? act 3 family revision 3 3-25 notes: 1. all unlisted pin num bers are user i/os. 2. nc denotes no connection. 3. mode should be terminated to gnd through a 10k resist or to enable actionprobe us age; otherwise it can be terminated directly to gnd. 4. the pg100 package has been discontinued. pg100 a1415 function location clka or i/o c7 clkb or i/o d6 dclk or i/o c4 gnd c3, c6, c9, e9, f3, f9, j3, j6, j8, j9 hclk or i/o h6 ioclk or i/o c10 iopcl or i/o k9 mode c2 pra or i/o a6 prb or i/o l3 sdi or i/o b3 sdo l9 vcc b6, b10, e11, f2, f10, g2, k2, k6, k10
package pin assignments 3-26 revision 3 pg133 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx note: this is the top view. 133-pin cpga a b c d e f g h j k l m n a b c d e f g h j k l m n 1 2 3 4 5 6 7 8 9 10111213 1 2 3 4 5 6 7 8 9 10 11 12 13
accelerator series fpgas ? act 3 family revision 3 3-27 notes: 1. all unlisted pin num bers are user i/os. 2. nc denotes no connection. 3. mode should be terminated to gnd through a 10k resist or to enable actionprobe us age; otherwise it can be terminated directly to gnd. 4. the pg133 package has been discontinued. pg133 a1425 function location clka or i/o d7 clkb or i/o b6 dclk or i/o d4 gnd a2, c3, c7, c11, c12, f10, g3, g11, l3, l7, l11, m3, n12 hclk or i/o k7 ioclk or i/o c10 iopcl or i/o l10 mode e3 nc a1, a7, a13, g1, g13, n1, n7, n13 pra or i/o a6 prb or i/o l6 sdi or i/o c2 sdo m11 vcc b2, b7, b12, e11, g2, g12, j2, j12, m2, m7, m12
package pin assignments 3-28 revision 3 pg175 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx note: this is the top view. a 1 bcdefghj kl 2 3 4 5 6 7 8 9 10 11 175-pin cpga abcdefghjkl m m n n p p r r 12 13 14 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
accelerator series fpgas ? act 3 family revision 3 3-29 notes: 1. all unlisted pin num bers are user i/os. 2. nc denotes no connection. 3. mode should be terminated to gnd through a 10k resist or to enable actionprobe us age; otherwise it can be terminated directly to gnd. 4. the pg175 package has been discontinued. pg175 a1440 function location clka or i/o c9 clkb or i/o a9 dclk or i/o d5 gnd d4, d8, d11, d12, e4, e14, h4, h12, l4, l12, m4, m8, m12 hclk or i/o r8 ioclk or i/o e12 iopcl or i/o p13 mode f3 nc a1, a2, a15, b2, b3, p2 , p14, r1, r2, r14, r15 pra or i/o b8 prb or i/o r7 sdi or i/o d3 sdo n12 vcc c3, c8, c13, e15, h3, h13, l1, l14, n3, n8, n13
package pin assignments 3-30 revision 3 pg207 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx note: this is the top view. 1 a b c d e f g h j k l m n p r s t 234567891011121314151617 1234567891011121314151617 a b c d e f g h j k l m n p r s t 207-pin cpga
accelerator series fpgas ? act 3 family revision 3 3-31 notes: 1. all unlisted pin num bers are user i/os. 2. nc denotes no connection. 3. mode should be terminated to gnd through a 10k resist or to enable actionprobe us age; otherwise it can be terminated directly to gnd. pg207 a1460 function location clka or i/o k1 clkb or i/o j3 dclk or i/o e4 gnd c14, d4, d5, d9, d14, j4, j 14, p3, p4, p7, p9, p14, r15 hclk or i/o j15 ioclk or i/o p5 iopcl or i/o n14 mode d7 nc a1, a2, a16, a1 7, b1, b17, c1, c2, s1, s3 , s17, t1, t2, t16, t17 pra or i/o h1 prb or i/o k16 sdi or i/o c3 sdo p15 vcc b2, b9, b16, d11, j2, j16, p12, s2, s9, s16, t5
package pin assignments 3-32 revision 3 pg257 note for package manufacturing and environmental information, visit the resource center at http://www.microsemi.com/soc/pr oducts/solutions/package/docs.aspx note: this is the top view. a b c d e f g h j k l m n p r t v x y a b c d e f g h j k l m n p r t v x y 12345678910111213141516171819 1 2 3 4 5 6 7 8 9 10 1112 13141516 1718 19 257-pin cpga
accelerator series fpgas ? act 3 family revision 3 3-33 notes: 1. all unlisted pin num bers are user i/os. 2. nc denotes no connection. 3. mode should be terminated to gnd through a 10k resist or to enable actionprobe us age; otherwise it can be terminated directly to gnd. pg257 a14100 function location clka or i/o l4 clkb or i/o l5 dclk or i/o e4 gnd b16, c4, d4, d10, d16, e11, j5, k4, k16, l15, r4, t4, t10, t16, t17, x7 hclk or i/o j16 ioclk or i/o t5 iopcl or i/o r16 mode a5 nc e5 pra or i/o j1 prb or i/o j17 sdi or i/o b4 sdo r17 vcc c3, c10, c13, c17, k3, k17, v3, v7, v1 0, v17, x14

revision 3 4-1 4 ? datasheet information list of changes the following table lists critical changes that were made in each version of the datasheet. revision changes page revision 3 (january 2012) the description for sdo pins had earlier been removed from the datasheet and has now been included again, in the "pin descript ions" section (sar 35820). 2-21 sdo pin numbers had earlier been removed from package pin assignment tables in the datasheet, and have now been restored to the pin tables (sar 35820). 3-1 revision 2 (september 2011) the act 3 datasheet was formatted newly in the style used for current datasheets. the same information is present (other t han noted in the list of changes for this revision) but divided into chapters. n/a the datasheet was revised to note in multiple places that speed grades ?2 and ?3 have been discontinued. the following device/package combinations have been discontinued for all speed grades a nd temperatures (sar 33872): a1415 pg100 a1425 pg133 a1440 pg175 a1460 bg225 refer to pdn 0104 , pdn 0203 , pdn 0604, and pdn 1004 . i and others the "features" section was revised to state the clock-to-ouput time and on-chip performance for ?1 speed grade as 9.0 ns and 186 mhz. the "general description" section was revised in accordance (sar 33872). i the maximum performance values were updated in table 1 ? act 3 family product information , and now reflect worst-case commercial for the ?1 speed grade (sar 33872). i the "product plan" table was updated as follows to conform to current offerings (sar 33872): the a1415a device is offered in pl84, pg100, and vq100 packages for military application. the a1440a device is offered in tq176 and vq100 packages for industrial application. iii table 1-1 ? chip-to-chip perf ormance (worst-case commercial) was updated to include data for all speed grades instead of only ?3 (sar 33872). 1-2 figure 1-1 ? predictable performance (worst-case commercial, ?1 speed grade) was revised to reflect values for the ?1 speed grade (sar 33872). 1-1 figure 2-10 ? timing model was updated to show data for the ?1 speed grade instead of ?3 (sar 33872). 2-16 table 2-14 ? logic module and routing delay by fanout (ns); worst-case commercial conditions was updated to include data for all speed grades instead of only ?3 (sar 33872). 2-20 package names used in the "package pin assignments" section and throughout the document were revised to match standards given in package mechanical drawings (sar 27395). 3-1
datasheet information 4-2 revision 3 revision 2 (continued) in the "package pin assignments" section , notes were added to the pin tables for the following packages, stating that they are discontinued: "bg225" "pg100" "pg133" "pg175" 3-20 3-24 3-26 3-28 revision 1 (june 2006) rohs compliant information was added to the "ordering information" section . ii revision changes page
accelerator series fpgas ? act 3 family revision 3 4-3 datasheet categories categories in order to provide the latest information to des igners, some datasheet parameters are published before data has been fully characterized from silicon devices. the data provided for a given device is designated as either "product brief," "advance," "pre liminary," or "production." the definitions of these categories are as follows: product brief the product brief is a summarized version of a data sheet (advance or producti on) and contains general product information. this document gives an overvi ew of specific device and family information. advance this version contains initial estimated information bas ed on simulation, other products, devices, or speed grades. this information can be used as estimates, bu t not for production. this label only applies to the dc and switching characteristics chapter of the da tasheet and will only be used when the data has not been fully characterized. preliminary the datasheet contains information based on simulation and/or initial characterization. the information is believed to be correct, but changes are possible. production this version contains information that is considered to be final. export administration regulations (ear) the products described in this document are subj ect to the export administ ration regulations (ear). they could require an approved export license prior to export from the united st ates. an export includes release of product or disclosure of technology to a foreign national inside or outside the united states. safety critical, life support, and high-reliability applications policy the products described in this advance status document may not have completed the microsemi qualification process. products may be amended or enhanced during the product introduction and qualification process, resulting in changes in device functionality or performance. it is the responsibility of each customer to ensure the fitne ss of any product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. consult the microsemi soc products group terms and conditions for specific liability exclusions relating to life-support applications. a reliability report covering all of the soc products group?s products is available at http://www.microsemi.com/s oc/documents/ort_report.pdf . microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures. contact your local sales office for additional reliability information.
5172106-3/1.12 ? 2012 microsemi corporation. all rights reserved. microsemi and the microsemi logo are trademarks of microsemi corporation. all other trademarks and service marks are the property of their respective owners. microsemi corporation (nasdaq: mscc) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security ; enterprise and communications; and industrial and alternative energy markets. products incl ude high-performance, high-reliability analog and rf devices, mixed signal and rf integrated circuits, customizable socs, fpgas, and complete subsystems. microsemi is headquarter ed in aliso viejo, calif. learn more at www.microsemi.com . microsemi corporate headquarters one enterprise, aliso viejo ca 92656 usa within the usa: +1 (949) 380-6100 sales: +1 (949) 380-6136 fax: +1 (949) 215-4996

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